Browse Prior Art Database

Multiple-Instruction Multiple-Data Programming of Pseudo-Multiple-Instruction Multiple-Data Parallel Process

IP.com Disclosure Number: IPCOM000116887D
Original Publication Date: 1995-Nov-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Dillinger, TE: AUTHOR [+2]

Abstract

A method for executing distinct programs on each processor of a Multiple-Data-Multiple-Instruction (MIMD) computer system is disclosed. This disclosure particularly addresses MIMD systems configured in hardware and/or software so as to load and execute the same initial binary on all processors. The disclosure assumes that each processor has an independent instruction memory and program counter.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Multiple-Instruction Multiple-Data Programming of Pseudo-Multiple-Instruction
Multiple-Data Parallel Process

      A method for executing distinct programs on each processor of a
Multiple-Data-Multiple-Instruction (MIMD) computer system is
disclosed.  This disclosure particularly addresses MIMD systems
configured in hardware and/or software so as to load and execute the
same initial binary on all processors.  The disclosure assumes that
each
processor has an independent instruction memory and program counter.

      Some highly parallel and massively parallel processor systems
have many characteristics of MIMD architectures, including a distinct
program counter and instruction memory per processing element, yet do
not directly allow a distinct program to run on each of the
processing elements.

      While such processor systems are very useful when executing
programs written in a data-parallel style (perhaps facilitated by a
data parallel programming language such as C*), execution of programs
written with irregular parallelism is difficult and inefficient.
Languages such as Ada, VHDL, and Concurrent C++ facilitate such an
irregular parallel programming style.

      In order to execute programs written in an irregular parallel
programming style, each processor must often be loaded with and
execute a distinct instruction sequence.  Loading the distinct
instruction sequences used by each processor into the instruction
memory of all processors, then branching to a processor-specific
entry point works, but makes very inefficient use of memory.

      True irregular parallel programming styles can be effi...