Browse Prior Art Database

Industry Standard SIMM with Option to Populate with 2-CAS or with Quad-CAS for Parity

IP.com Disclosure Number: IPCOM000116894D
Original Publication Date: 1995-Nov-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Csonka-Peeren, JV: AUTHOR [+2]

Abstract

There is disclosed an industry standard 1Mx36 SIMM with word-wide access which can be populated with either two 1Mx2-2CAS DRAM modules or one 1Mx4-QuadCAS DRAM module.

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Industry Standard SIMM with Option to Populate with 2-CAS or with
Quad-CAS for Parity

      There is disclosed an industry standard 1Mx36 SIMM with
word-wide access which can be populated with either two 1Mx2-2CAS
DRAM modules or one 1Mx4-QuadCAS DRAM module.

      The Figure shows the block diagram of a 1Mx36 industry standard
SIMM with word-wide access.  U2 and U4 share enough common control
and data lines with U3 such that the parity SIMM can populated with
either two 1Mx2-2CAS DRAM modules (U2 and U4) or one 1Mx4-QuadCAS
DRAM
modules (U3), without change in the intended function of the design.

      The control lines CAS0* and CAS1*, and the data lines DQ8 and
DQ17 are shared between U3 and U4.  The control lines CAS1* and
CAS2*, and the data lines DQ26 and DQ35 are shared between U3 and U2.
As per industry standard, RAS0* and RAS2* are activated concurrently
during a word-wide (36-bit) access.  Therefore, RAS2* is used to
control row address strobing for U2 and U3, while RAS0* is used for
U4.

      When the SIMM uses 2CAS DRAM modules for parity, only the sites
for U1 U2 U4 and U5 are populated, while the site for U3 remains
unpopulated.  When the SIMM uses QuadCAS DRAM modules for parity,
only the sites for U1 U3 and U5 are populated, while the sites for U2
and U4 remain unpopulated.