Browse Prior Art Database

Pre-Physical Design Capacitance and Resistance/Capacitance Estimation using Pin Connection Types

IP.com Disclosure Number: IPCOM000116904D
Original Publication Date: 1995-Nov-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 111K

Publishing Venue

IBM

Related People

Edwards, MK: AUTHOR [+4]

Abstract

Disclosed is a method for improving the accuracy of pre-placement net capacitance and Resistance/Capacitance (RC) delay estimates by using information available about the types of logic pins connected to the net. The idea is this: certain types of nets may have more, or less capacitance and delay than other types of logic nets. For example, bit-stack nets are typically shorter than average nets, and global nets are typically longer than average. So, if knowledge can be obtained about the type of the net in question, and about the typical characteristics for this type of net, then this knowledge can be used to improve the accuracy of the net capacitance and RC delay estimates for the net. This can be done as described below.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Pre-Physical Design Capacitance and Resistance/Capacitance Estimation
using Pin Connection Types

      Disclosed is a method for improving the accuracy of
pre-placement net capacitance and Resistance/Capacitance (RC) delay
estimates by using information available about the types of logic
pins connected to the net.  The idea is this:  certain types of nets
may have more, or less capacitance and delay than other types of
logic nets.  For example, bit-stack nets are typically shorter than
average nets, and global nets are typically longer than average.  So,
if knowledge can be obtained about the type of the net in question,
and about the typical characteristics for this type of net, then this
knowledge can be used to improve the accuracy of the net capacitance
and RC delay estimates for the net.  This can be done as described
below.

      First, knowledge must be gathered about different types of
logical nets and the capacitance and/or RC characteristics for those
types of nets.  This knowledge can be gathered from a variety of
available sources, including device-level simulation and physical
data extraction from similar chips which have already been placed and
wired.  This information could then be placed into a database, if
desired, for easy access by capacitance and RC estimation programs.

      Then, improved estimates can be made for a net in question, by
determining the type of the net and simply setting the capacitance
and RC delay estimates to appropriate values for that type of net, as
determined by the information gathered in the previous step.

      An extension to this idea is to gather information about how
different types of logical net connections (pins) contribute to net
capacitance and delay.  This information can be placed into a
database and subsequently used to calculate improved capacitance and
RC estimates for other nets.  The estimates for a new net could be
derived by determining the types of logical connections on the net
and then by using the previously gathered information about how the
specific connection types contribute to net capacitance and RC delay.

      Another useful extension to this idea is that it can be used to
give different estimates to nets from different design partitions.
For example, all nets in a partition of bitstack logic could have
different capacitance and RC estimates than nets belonging to some
other logic partition.  This can be easily implemented by putting
separate values into the database for different logic partitions, and
then by querying the database using the partition and/or the net
connection types as database indices.

      These ideas could be implemented in many ways. ...