Browse Prior Art Database

Tracing Hardware for a Multiplexed Interface

IP.com Disclosure Number: IPCOM000116909D
Original Publication Date: 1995-Nov-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 99K

Publishing Venue

IBM

Related People

Gregg, TA: AUTHOR [+2]

Abstract

Disclosed is a method of tracing hardware used to record events on an I/O interface for the purposes of troubleshooting problems. Message handling facilities in the channel allow a number of messages to be multiplexed over the I/O interface, and the storage in the tracing hardware is divided into multiple areas, one area for each message handler. The tracing hardware examines the messages and their responses, extracts the information to be recorded, and writes it into the proper area of its storage.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Tracing Hardware for a Multiplexed Interface

      Disclosed is a method of tracing hardware used to record events
on an I/O interface for the purposes of troubleshooting problems.
Message handling facilities in the channel allow a number of messages
to be multiplexed over the I/O interface, and the storage in the
tracing hardware is divided into multiple areas, one area for each
message handler.  The tracing hardware examines the messages and
their responses, extracts the information to be recorded, and writes
it into the proper area of its storage.

      Built in interface trace hardware is useful for gathering
'first error data capture' information when debugging problems,
because external trace tools are not required, and the bug does not
have to be recreated.  Interface trace hardware usually contains some
kind of filter that determines which events are significant for
tracing, a time stamp, and storage for keeping the traced
information.

      This disclosure relates to the message channel described in
(*).  In this channel, there are multiple buffer sets, each of which
operates independ ently.  Each buffer set is capable of handling one
message.  The interface tracing hardware allocates its tracing
storage so that each buffer set has its own independent area.
Dividing the storage into multiple areas prevents high activity of
one buffer set from filling all of the storage and thus loosing trace
information for the other buffer sets.  The tracing hardware has four
modes of operation.  Two of the modes are used for tracing internal
hardware facilities, and the other two modes are used for tracing the
outbound and inbound I/O interfaces.  Only one of the interface trace
modes is described.

      The Figure shows the organization of the tracing hardware when
used in normal interface trace mode.  There are four address
registers called ORIG 0 ADR, ORIG 1 ADR, RECIP 0 ADR, and RECIP 1 ADR
that can be set to zero or incremented by one.  Each address register
is used by one of the four buffer sets that are called originate 0,
originate 1, recipient 0, and recipient 1, respectively.  The address
registers feed a four way multiplexer whose output provides the low
order address bits to the trace storage.  The contents of the address
registers can also be read by a microcontroller that logs the trace
information.  The data inputs to the trace storage consist of an
eight bit control value, a 24 bit timer value, and 32 bits of
interface infor...