Browse Prior Art Database

Cache Lock Operation Control for Personal Computers

IP.com Disclosure Number: IPCOM000116921D
Original Publication Date: 1995-Nov-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 218K

Publishing Venue

IBM

Related People

Lenta, JE: AUTHOR [+2]

Abstract

Described is an architectural implementation to provide a Cache Lock Operation Control (CLOC) function for Personal Computers (PCs). The CLOC is designed to synchronize hardware and software metaphors that require total system data control properly, so that only one user has access to the system at any one time.

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This is the abbreviated version, containing approximately 28% of the total text.

Cache Lock Operation Control for Personal Computers

      Described is an architectural implementation to provide a Cache
Lock Operation Control (CLOC) function for Personal Computers (PCs).
The CLOC is designed to synchronize hardware and software metaphors
that require total system data control properly, so that only one
user has access to the system at any one time.

      The CLOC can be optionally installed in PC systems to
facilitate the use of second level store-in cache controllers.  Its
use allows increased overall system performance and maintains data
integrity when microprocessor lock cycles are executed, as performed
in devices such as the Intel* 486 microprocessor.  The CLOC is
designed to be a complete secondary cache subsystem for use with
Intel i486* type of central processing units (CPUs), or CPUs that
have similar bus interfaces.  The CLOC allows for features, such as
the look aside store in cache controller (LASICC) to be connected to
the system directly, or by means of a pluggable connector.

      The cache offers the flexibility of write-back and
write-through operations and is designed to supply data to the CPU in
zero wait states for cache read hit bus cycles and to accept data
from the CPU in zero wait states for cache read hit bus cycles.  It
can also accept data from the CPU in zero wait states for write
cycles which hit a write-back cache line.

      Fig. 1 shows a block diagram of the use of CLOC along with the
LASICC in a system.  CPU 10 contains first level CPU cache 11 and is
connected to memory controller 13 and memory units 15 through data
bus 12.  LASICC 14 connects to data bus 12 through the CLOC
interconnect signal protocol 17.  This protocol defines the LASICC
operation with CPU 10 and memory controller 13 using control signals
16.  The CLOC provides five basic functions as follows:
   --  Memory Write - The cache recognizes the start of a write
    cycle such that the type of write operation is based on an
    internal write-back/write-through flag that is stored with each
    cache line.  As soon as the address is valid at the input of the
    cache, the cache begins its tag and status look-up.  The cache
    will handle the processing of the write cycle based on whether
    the line is contained within the cache and also on the value of
    the status flags associated with the line.
   --  Memory Write Through Hit - A line which is in the cache is
    treated as a write through hit if either the page write through
    (PWT) input is high, or the page cache disable (PCD) input is
    high, or the cacheline's write through status bit is set.  The
    cache can accept a snoop and invalidation cycle request during a
    write to a write through line.  If the line is not marked dirty,
    the valid bit for the cache line will be cleared.  It is
    anticipated that the Read Only Memory (ROM) space will be marked
    as write-t...