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Method and Apparatus for Handling Multiple Clock Domain at Speed Logic Built-In Self-Test within a Single Logic Built-In Self-Test Structure

IP.com Disclosure Number: IPCOM000116934D
Original Publication Date: 1995-Nov-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Douskey, SM: AUTHOR [+2]

Abstract

As chip sizes increase the likelihood of multiple clock domains on a single chip increase as well. If at-speed (AC) Logic Built-In Self-Test (LBIST) is used, a method for handling these multiple clock domains must be conceived. A practical solution is presented below.

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This is the abbreviated version, containing approximately 71% of the total text.

Method and Apparatus for Handling Multiple Clock Domain at Speed
Logic Built-In Self-Test within a Single Logic Built-In Self-Test
Structure

      As chip sizes increase the likelihood of multiple clock domains
on a single chip increase as well.  If at-speed (AC) Logic Built-In
Self-Test (LBIST) is used, a method for handling these multiple clock
domains must be conceived.  A practical solution is presented below.

      Here are two solutions implemented for running LBIST on chips
with multiple clock domains (multiple oscillator inputs).  One for
clock domains that are at very close to the same rate, and one for
very different rate domains.

      If the clocks are at nearly the same rate, the total LBIST can
be run from one oscillator with very little AC coverage loss in each
section.  Clock logic handles this with a simple AND*OR, with LBIST
Mode as the gate.

      When the clocks are at much different rates, LBIST is run to
each domain individually, with the other domain disabled.  In this
manner, all domains are tested internally at the rate they are being
used in the system and all interfaces between domains are tested as
static (DC).  Also the ring selection does not change, the whole chip
is still scanned though only part is really tested at any one time.

      The clock logic is able to single cycle different rate clocks
from the same LBIST logic interface by synchronizing a run clocks
pulse.  The Figure shows one method for capturing a...