Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Multiple Preamble/Address Mark Format

IP.com Disclosure Number: IPCOM000116952D
Original Publication Date: 1995-Dec-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Kanai, T: AUTHOR [+3]

Abstract

This article describes about an Hard Disk Drive which has multiple preamble (SYNC) and Address Mark (SYNC BYTE) track formats. If there is a large missing bits and/or large extra bits at the SYNC and/or SYNC BYTE location, single preamble and single address mark track format cause Phase Lock Loop (PLL) malfunction and caused burst error. This method is to have multiple preamble and address mark on the track format, and recover the error location in Error Recovery Procedure (ERP).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Multiple Preamble/Address Mark Format

      This article describes about an Hard Disk Drive which has
multiple preamble (SYNC) and Address Mark (SYNC BYTE) track formats.
If there is a large missing bits and/or large extra bits at the SYNC
and/or SYNC BYTE location, single preamble and single address mark
track format cause Phase Lock Loop (PLL) malfunction and caused burst
error.  This method is to have multiple preamble and address mark on
the track format, and recover the error location in Error Recovery
Procedure (ERP).

      The Figure shows the one of the implementation of this
algorithm.  If there is a large missing bits (a), HDC is skipping
certain number of Read Reference Clock (RRCK) after SYNC_BYTE_1(SB1)
is detected, and start the read operation at Data (0) location.

      If there is a large missing bits (b), Micro code will use
delayed Read Gate at SYNC2 location, and start the read operation if
SYNC_BYTE_2(SB2) is detected.

      The benefit of this method is minimizing the disturbance of the
read back signal which cause the malfunction of PLL, and also
applicable
for Read/Write channel which has own SYNC BYTE (ex. PRML channel).