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Zero Delay Synchonizer

IP.com Disclosure Number: IPCOM000116953D
Original Publication Date: 1995-Dec-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 92K

Publishing Venue

IBM

Related People

Bland, PM: AUTHOR [+8]

Abstract

Using unsynchronized inputs in a synchronous state machine does not work due to metastability when setup or hold times are violated. It is common to run the unsynchronized input through at least one, but often two levels of latching to synchronize the edge to the reference clock. There are times, however, when the resulting two clock delay will move the edge too far out in time for the proper operation of the circuit; for example, perhaps cutting too far into a data hold time.

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This is the abbreviated version, containing approximately 52% of the total text.

Zero Delay Synchonizer

      Using unsynchronized inputs in a synchronous state machine does
not work due to metastability when setup or hold times are violated.
It is common to run the unsynchronized input through at least one,
but often two levels of latching to synchronize the edge to the
reference clock.  There are times, however, when the resulting two
clock delay will move the edge too far out in time for the proper
operation of the circuit; for example, perhaps cutting too far into a
data hold time.

      Very often, the rising edge of an active low control signal is
the edge used to latch data.  This invention, referred to as a Zero
Delay Synchronizer (ZDS), provides a way to synchronize the rising
edge of a pulse without paying the usual one or two clock
synchronization penalty.  The idea is that, by knowing the
approximate shape of the input pulse, you can anticipate the rising
edge by using a state machine to generate that edge synchronously,
without waiting for the actual input edge.  This can be accomplished
on standard busses because cycle lengths are defined by the standard
and are thus known.  You also know data setup and hold times, so you
know how long or short you can shape the pulse and still meet
timings.

      See Fig. 1.  MEMW* is the signal that needs to be synchronized
in the Figure.  First note that the standard method of
synchronization,
represented by the signal SYNC*, fails in this case due to the amount
of DATA hold time from the rising edge of MEMW* --
the data has switched BEFORE the rising edge of SYNC*.  Therefore,
even though the goal of synchronization has been achieved, the
resulting signal is unusable because it is delayed too much and has
latched invalid data.

      Now refer to the signal called ZERO_SYNC*, which is the output
of the ZDS.  Its falling edge combinatorially flows through and is
not synchronized since the falling edge is not used for latching
(i.e., this edge does not need to be synchronized).  The rising edge
is generated after a fixed number of clocks by the ZDS' state machine
and actually occurs before the rising edge of MEMW*.  Note that the
rising edge of ZERO_SYNC* is not only synchronous to the clock, but
it meets both the setup and hold time for the DATA.

      The only other situation that needs to be handled is target
inserted wait states.  The ZDS detects if wait states are being
inserted and holds off the rising edge of ZERO_SYNC* until the wait
states are over.

      Fig. 2 shows a block diagram of how to interface the Zero Delay
Synchronizer to...