Browse Prior Art Database

System Electronic Packaging Architecture

IP.com Disclosure Number: IPCOM000116954D
Original Publication Date: 1995-Dec-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 76K

Publishing Venue

IBM

Related People

Frankeny, JA: AUTHOR

Abstract

Disclosed is a method to produce the most efficient wiring of several Ball Grid Array (BGA) devices together in a Multi Chip Module (MCM). The shortest distance between two or more Single Chip Modules (SCM) is thru the substrate and all that is necessary is a process to attach SCM's on top and bottom of the substrate. Fig. 1 is just such a substrate manufactured using present state-of-the-art flexible multi layer substrate. The top SCM (14) and the bottom SCM (11) are BGA devices (12) and (13). The center plane is a power plane (16) made with the present state-of-the-art. It has power vias (5), signal vias (1) and ground vias (6). The complete composite has signal connector (8) and (18) made using state-of-the-art area array connectors with IBM* dendritic interfaces.

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System Electronic Packaging Architecture

      Disclosed is a method to produce the most efficient wiring of
several Ball Grid Array (BGA) devices together in a Multi Chip Module
(MCM).  The shortest distance between two or more Single Chip Modules
(SCM) is thru the substrate and all that is necessary is a process to
attach SCM's on top and bottom of the substrate.  Fig. 1 is just such
a substrate manufactured using present state-of-the-art flexible
multi layer substrate.  The top SCM (14) and the bottom SCM (11) are
BGA devices (12) and (13).  The center plane is a power plane (16)
made with the present state-of-the-art.  It has power vias (5),
signal vias (1) and ground vias (6).  The complete composite has
signal connector (8) and (18) made using state-of-the-art area array
connectors with IBM* dendritic interfaces.  The power connection is
separate from the signal connection.  The via spacing will be the
same as the BGA (10), (12), and (13).  Each layer (15), (16), (17) is
made and tested before lamination following state-of-the-art
processes.

      Each SCM has the I/O's that are going to the other SCM in a
specific area as shown in Fig. 2.  The shaded area is the I/O's and a
simular maching are a is on the mating SCM.

      For a two SCM version, the I/O shaded areas are lined up over
each other and the distance between them is just the thickness of the
substrate.  The present state-of-the-art substrates and assembly
processes can be used to m...