Browse Prior Art Database

The Helix Switch: Single Chip Asynchronous Transfer Mode Switch Architecture

IP.com Disclosure Number: IPCOM000116955D
Original Publication Date: 1995-Dec-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 103K

Publishing Venue

IBM

Related People

Patel, BV: AUTHOR [+3]

Abstract

A VLSI architecture for a high speed, non-blocking, cell switch is proposed. The architecture is particularly well suited for VLSI implementation, and is scalable to support many connections at high data rates. The switch employs a self-routing shift register ring design to transfer cells between the inputs and the outputs, and utilizes an efficient shared buffer scheme at the output. The shift register ring design is advantageous from a VLSI standpoint because it uses short interconnections, low fan-out for the gates, and very few levels of logic, thus reducing the delay, and area; a critical requirement for a high band width switch. Furthermore, the switch is designed using dynamic latches which require very small area.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

The Helix Switch: Single Chip Asynchronous Transfer Mode Switch Architecture

      A VLSI architecture for a high speed, non-blocking, cell switch
is proposed.  The architecture is particularly well suited for VLSI
implementation, and is scalable to support many connections at high
data rates.  The switch employs a self-routing shift register ring
design to transfer cells between the inputs and the outputs, and
utilizes an efficient shared buffer scheme at the output.  The shift
register ring design is advantageous from a VLSI standpoint because
it uses short interconnections, low fan-out for the gates, and very
few levels of logic, thus reducing the delay, and area; a critical
requirement for a high band width switch.  Furthermore, the switch is
designed using dynamic latches which require very small area.  Thus,
the shift register ring provides a compact, low delay interconnection
fabric for high throughput switching.  Since the shift register ring
serializes (pipelines) the delivery of cells to the destination, the
concurrent cells destined for the same output arrive in an
interleaved fashion.  Thus, the helix switch resolves output
contention by serializing the delivery of cells without impacting
performance.  Furthermore, the ring design is a very effective means
of supporting multicast and broadcast.  The details of the
implementation and performance evaluation of a single-chip VLSI
design of a 16-port (1Gbps/sec per port) ATM switch, based on the
Helix architecture, are presented in this paper.

The helix switch has four primary components: 1) Line interface
modules, 2) Shirt register switch fabric, and 3) output buffers.

        The Line interface modules.  The Line Interface Module (LIM)
at the input links of the ATM node receives a serial bit stream from
the link and converts it into a parallel sequence of bytes or words.
Furthermore, the cell label is processed in the LIM to identify the
output port onto which the cell has to be transmitted.  The output
port address is prepended to the ATM cell and the cell is then
forwarded to the helix switch.  The helix switch then routes the cell
to the appropriate output port as indicated by the prepended output
port address.  The ATM cell is converted into a bit-stream and
transmitted on the output link.

        The shift register switch fabric.  The Helix switch is based
on a shift register ring interconnection.  It connects a set of N
input ports (IP0,IP1,...,IPn-1) to N output ports (OP0,
OP1,...,OPn-1).  It consists of N shift register stages (R0,
R1,...,Rn-1) connected in a ring topology.  Each input IPi is
connected to the shift register stage Ri and each output OPi is
directly connected to shift register stage Ri-1.  Both, the input
ports and output port...