Browse Prior Art Database

Self Resetting CMOS Receiver

IP.com Disclosure Number: IPCOM000116958D
Original Publication Date: 1995-Dec-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 81K

Publishing Venue

IBM

Related People

Cao, TA: AUTHOR [+5]

Abstract

High speed or fast cycle time state-of-the-art microprocessors will attempt to latch the incoming signal as soon as possible because the signal is coming from off chip where most of the cycle time is consumed by wire delay on the printed board or multi-chip-module.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Self Resetting CMOS Receiver

      High speed or fast cycle time state-of-the-art microprocessors
will attempt to latch the incoming signal as soon as possible because
the signal is coming from off chip where most of the cycle time is
consumed by wire delay on the printed board or multi-chip-module.

      Before the incoming signal reaches the latch, it must go
through a receiver circuit which detects the signal for proper
voltage
level and rejects false signals caused by noise.  This introduces
undesirable receiver delay that could be used for other purposes.

      This disclosure proposes to eliminate the separate receiver and
use the first useful logic circuit as a receiver, which in most cases
is a latch using the CMOS self-resetting-circuit designs.

      The problem with using the latch (or any internal logic
circuit) as a receiver is that the down level does not have adequate
noise margin.  This disclosure proposes a solution to improve the
down level noise margin.

      Fig. 3 shows the schematic of the disclosed invention.  This is
a new version of the dynamic self-resetting circuit with an improved
input noise margin that allows it to operate as a receiver of
off-chip
signals.  This effectively saves a stage of delay by combining these
functions as opposed to a separate receiver and latch in series.

      The N-type devices Q4 & Q5 shown in Fig. 3 are in series with
their inputs tied to the EVALUATE signal.  The PRECHARGE or the RESET
signal...