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Method for Calculating Buffer Size to Support Simultaneous Transfers

IP.com Disclosure Number: IPCOM000116993D
Original Publication Date: 1995-Dec-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 6 page(s) / 181K

Publishing Venue

IBM

Related People

Nostrand, M: AUTHOR

Abstract

The purpose of this article is to describe a heuristic method for calculating internal buffer sizes of a three ported bus interface device while maintaining bandwidth requirements of the device. The method makes the following assumptions of the bus interface device: o Three ported device o One port provides the bus interface o Two local ports share the bus interface port o Bandwidth requirements of the bus interface stem from sum of local port peak bandwidths

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This is the abbreviated version, containing approximately 24% of the total text.

Method for Calculating Buffer Size to Support Simultaneous Transfers

      The purpose of this article is to describe a heuristic method
for calculating internal buffer sizes of a three ported bus interface
device while maintaining bandwidth requirements of the device.  The
method makes the following assumptions of the bus interface device:
  o  Three ported device
  o  One port provides the bus interface
  o  Two local ports share the bus interface port
  o  Bandwidth requirements of the bus interface stem from sum of
      local port peak bandwidths

      The method described in this article will satisfy peak
bandwidths of both local ports while efficiently utilizing the buffer
size of the two internal buffers.

      In the past, there has been a need for a given bus agent to
transfer large amounts of data to different locations over a bus
simultaneously.  Each transfer must be done in an efficient manner to
maintain the bandwidth of each data path.  For instance, a graphics
adapter must accept graphics commands and data from the host.
Concurrently, it must often transfer pixel data to or from the host.
Each of these transfers has a required minimum bandwidth to maintain
the graphics adapter performance.  It may also be a design point of
the graphics adapter to have the pixel bus separate from the graphics
command/data bus.  It is the responsibility of the interface chip to
meet these bandwidth requirements for the two separate busses.

      A solution for maintaining dual transfers is to interleave on
the interface bus while still maintaining the proper bandwidth for
each transfer over the local busses.  This solution implies that the
interface chip must have buffering to maintain data transfers to one
data path while it is transferring data for the other path over the
bus.  Refer to the Figure.

      Historically, these buffers have been as large as the interface
chip silicon would allow.  This would try to insure the bandwidth was
maintained.  Hopefully, simulation would prove or disprove the buffer
size choice.

      The algorithm described in the solution section guarantees that
the bandwidth requirements for the two data paths will be met while
using the minimum buffer size to achieve these requirements.  This
gives the interface chip designer knowledge at the beginning of the
design of the feasibility of maintaining dual transfers and the
required buffer size to achieve the bandwidth of each transfer.

      This algorithm finds the minimum buffer sizes to support dual
transfers over the interface while maintaining bandwidth requirements
for each data path.  The interface chip has three ports: bus
interface, local port x, and local port y.  Local ports x and y s are
the bus interface to transfer data.  Refer to Fig. 1.

This algorithm requires the following inputs:
  bus interface peak transfer rate (bus bandwidth or bus_bw)
  bus latency for transferring first data item (b...