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Single-Ended Sense Amplifier Noise Suppressor

IP.com Disclosure Number: IPCOM000116994D
Original Publication Date: 1995-Dec-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 62K

Publishing Venue

IBM

Related People

Lang, KW: AUTHOR [+3]

Abstract

A conventional single-ended sensing scheme is shown in Fig. 1. During precharge, Precharge and Sense Amp Enable are both low which allows the bitlines and both sides of the sense amp to charge up to Vdd. In preparation for a "read" operation, Precharge is then driven to a high level which floats the bit lines. When a wordline is selected, the bit line will either remain high for a "1" or drop below Vdd for a "0". After sufficient signal is developed across the sense amp, Sense Amp Enable is brought high to set the sense amp. Any small noise on the Vdd bus between the time that the bit lines are floated and Sense Enable becomes active could upset the sense amps and cause an error. This phenomena was observed on previous products.

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Single-Ended Sense Amplifier Noise Suppressor

      A conventional single-ended sensing scheme is shown in Fig. 1.
During precharge, Precharge and Sense Amp Enable are both low which
allows the bitlines and both sides of the sense amp to charge up to
Vdd.  In preparation for a "read" operation, Precharge is then driven
to a high level which floats the bit lines.  When a wordline is
selected, the bit line will either remain high for a "1" or drop
below Vdd for a "0".  After sufficient signal is developed across the
sense amp, Sense Amp Enable is brought high to set the sense amp.
Any small noise on the Vdd bus between the time that the bit lines
are floated and Sense Enable becomes active could upset the sense
amps and cause an error.  This phenomena was observed on previous
products.  The source of noise can be a global disturbance on the Vdd
bus, or by the setting of the sense amps themselves.  During the set
operation, a current path, together with any timing skew in the
arrival of Sense Amp Enable between the near end and far end sense
amps can cause failures, particularly in the far end sense amps.

      Fig. 2 shows the proposed improvement.  Capacitor C0 is
initially precharged to Vdd-SA = Vdd.  Since the presharge signal is
turned off before Sense Amp Enable goes active, there is a time when
the node Vdd-SA will be floating.  To prevent any significant changes
in the value of Vdd-SA during this time, pfet device T6 is added.
This device is always on...