Browse Prior Art Database

On-Chip Noise Reduction

IP.com Disclosure Number: IPCOM000117017D
Original Publication Date: 1995-Dec-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 77K

Publishing Venue

IBM

Related People

Folberth, H: AUTHOR [+4]

Abstract

Disclosed is a typical wiring structure in the last metal layer of a chip carrier (Fig. 1). Several signal lines are running in parallel adjacent to one single GND line. In this case 7 signal lines and GND line are shown. The worst case coupling situation happens if the quiet signal line is surrounded by 3 neighbor signal lines on each side, switching simultaneously and thereby couple into the quiet line.

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On-Chip Noise Reduction

      Disclosed is a typical wiring structure in the last metal
layer of a chip carrier (Fig. 1).  Several signal lines are running
in parallel adjacent to one single GND line.  In this case 7 signal
lines and GND line are shown.  The worst case coupling situation
happens if the quiet signal line is surrounded by 3 neighbor signal
lines on each side, switching simultaneously and thereby couple into
the quiet line.

      This structure leads to the highest coupled on chip noise as
shown in the Table.  The significant improvement is achieved with the
wiring structure 2 shown in Fig. 2, whereby each signal is surrounded
by GND shield lines or voltage shield lines from both sides.  The
chip image has to be modified accordingly and the automatic wiring
and placement programs have to support this structure.

      The reduction of OCD noise on coupled last metal wiring is
shown in the Table.  The wiring structures are described in Figs. 1
and 2.

Table 1: on-chip OCD noise
  wiring
                  Kc      Kl       Vne      Vfe
  structure
  structure 1    0.81     3.44     210mV    -130mV
  structure 2    0.03     0.15      10mV    -  7mV

      The near end and far end noise values are based on 5 mm
parallel on chip wiring, which is a realistic assumption for large
chips.  The coupling coefficients have been calculated by
3-dimensional L,C modeling programs.  The total sum of on chip
coupled
noise, assuming a near and reflecting coefficient of r = -0.5 is:
  Structure 1: 245 mV
  Structure 2:  12 mV

      Structure 2 shows a significant OCD noise reduction down to
negligible low OCD noise values!

      Wiring structure 2 also reduces the logic noise by
approximately 20 %.  This effect is generated by the decrease of the
ohmic resistances Rnwv and Rnwg, which connect to the NWELL
capacitance (C(nw)), the decrease of the resistances R(sv) and
R(sg), which connect to the on module capacitors.

      This l...