Browse Prior Art Database

Enforcement of Memory Access Ordering to Non-Coherency Data

IP.com Disclosure Number: IPCOM000117020D
Original Publication Date: 1995-Dec-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 139K

Publishing Venue

IBM

Related People

Aden, S: AUTHOR [+5]

Abstract

Disclosed is a method for enforcing the memory access ordering of non-coherent data with in a directory-based memory subsystem of a multiprocessor system.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 37% of the total text.

Enforcement of Memory Access Ordering to Non-Coherency Data

      Disclosed is a method for enforcing the memory access ordering
of non-coherent data with in a directory-based memory subsystem of a
multiprocessor system.

      Coherency is a term for Multiprocessors (MP).  In a single
processor (UP) system, no coherency issues need to be addressed.  In
a Symmetrical Multiprocessor (SMP) system, non-coherency is defined
in terms of "among processors"; the memory access order is not
guaranteed between processors.  However, from the same processor
point of view, its memory accesses (Reads and Writes) to the same
address have to be in order.  That is, a read can not bypass a
proceeding write.  If this were allowed, all consistency (ordering)
rules would be broken and no consistent result could be guaranteed.

      In PowerPC* processor designs, such as 603, 604, or 620, the
first access to a cache line results in a cache miss.  When the data
is loaded into the second level cache, the data is not marked to
indicate if the line requires coherency.  When time comes to purge
(replaced or cat out) a line, no coherency information can be
reported.  Thus, the WIM bits (of which the M bit, when asserted,
indicates coherency required) for the purge request are always set to
a constant value described in the processor's implementation
definition book IV.  The WIM bits are defined by the PowerPC
architecture and stand for write through cache, caching inhibited,
and memory coherence respectively.  The processor makes use of these
bits to determine the storage access mode for a memory page.  The
bits indicate the reason for the purge, but the coherency information
has been lost.  The result of this is that the memory must decode the
code point of the purge request and treat the request as a coherent
access to the memory even though the addressed location may not
require coherency.  The additional processing of an operation to a
location which did not require coherency checking opens the
possibility of other following operations which do indicate that
coherency is not required to bypass the operation undergoing the
additional processing.

      In a directory-based SMP, all requests requiring coherency must
be processed by Memory Directory Unit.  Requests which do not
indicate if coherency is or is not required can result in violating
consistency rules for the requests from a single processor.  This
method describes a method by which consistency rules can be
maintained without valid coherency information contained in a cast
out request.

      Let's examine a case which causes a stale non-coherency data
access in a directory-based SMP system.
  Time      System Action
  t1:       CPU0 issues a non-coherency Load Miss to address X
             (WIM=000).
  t2:       The non-coherency Load Miss arrives at memory controller
A.
  t3:       Memory controller A sets the non-coherency Load M...