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Error-Correction Code using Self Reset Approach

IP.com Disclosure Number: IPCOM000117023D
Original Publication Date: 1995-Dec-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 97K

Publishing Venue

IBM

Related People

Shah, KB: AUTHOR

Abstract

As technology advances toward larger memory arrays to gain higher performance, many issues are raised in the design and implementation of these memory arrays. Large memory arrays are even more prone to alpha particles and noise, and have a high single cell failure rate. This causes erroneous output data, which may lead to lower chip yields and lower system reliability. Significant improvement to the chip reliability and yield is obtained by implementing an Error Correction Code (ECC) on the SRAM.

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Error-Correction Code using Self Reset Approach

      As technology advances toward larger memory arrays to gain
higher performance, many issues are raised in the design and
implementation of these memory arrays.  Large memory arrays are even
more prone to alpha particles and noise, and have a high single cell
failure rate.  This causes erroneous output data, which may lead to
lower chip yields and lower system reliability.  Significant
improvement to the chip reliability and yield is obtained by
implementing an Error Correction Code (ECC) on the SRAM.

      An ECC circuit detects erroneous output data from the memory
array and corrects it.  The ECC circuit can be designed by the
following approaches: static and Self Reset (SR).  For high
performance SRAMs, it is becoming more difficult to achieve the ECC
function in one cycle time with the conventional static approach
without paying a penalty in critical data path by adding extra
pipeline stage.  The SR approach is the desired way to meet the high
performance, high yield requirements of SRAMs.  The main advantage of
SR approach is that the ECC circuit's output has a fixed access time
in critical data path, compared to access time of Static ECC circuit
on the SRAM chip is a critical factor in achieving high performance
requirements, regardless of which approach is used.  Problems such as
increased chip size and excessive chip delay occurs if the ECC
circuit is not optimally placed.

      This disclosure presents a design and implementation of
self-contained on chip SR ECC circuit embedded in the high speed
cache memory array.  Floor planning of the ECC is done before the
initial circuit design is done.

      The SR ECC circuit was designed to a...