Browse Prior Art Database

Pixel Selection Scheme for MOS Imager

IP.com Disclosure Number: IPCOM000117033D
Original Publication Date: 1995-Dec-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 95K

Publishing Venue

IBM

Related People

Dhong, S: AUTHOR [+3]

Abstract

Disclosed is a scheme for performing pixel selection in MOS imager arrays. The described implementation has the potential for improved performance over the present design.

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This is the abbreviated version, containing approximately 52% of the total text.

Pixel Selection Scheme for MOS Imager

      Disclosed is a scheme for performing pixel selection in MOS
imager arrays.  The described implementation has the potential for
improved performance over the present design.

      In current MOS imager designs of active pixel arrays, pixel
addressing is commonly accomplished by a selection transistors
located in the pixel (1,2,3).  It is placed in series with the pixel
output transistor thereby allowing the pixel to be either selected or
isolated.  A pixel circuit is shown in Fig. 1.  Q2 is the pixel
output transistor and QS is the pixel selection transistor.  In a
typical array, the output of many pixels would be connected in
parallel to a common bus.  With appropriate control of the selection
transistors, only one pixel would send its output to the bus at a
time.  The others would remain isolated.  By sequentially activating
the selection transistor in each pixel, all the pixels can share the
common output circuitry, sending their data out in serial fashion.

      The described addressing scheme is quite similar to that used
in Static Random Access Memory, (SRAM), arrays.  In SRAMs, however,
the performance of the selection transistor is not very critical
since the information being accessed is binary, therefore requiring
only to distinguish between one of two voltage levels.

      In a MOS imager array, the information is of an analog nature.
Therefore, the performance of the selection transistor in this
configuration can be more critical.  Specifically, the placement of
the selection transistor in series with the pixel output transistor
introduces an additional voltage drop in the output circuit.  The
magnitude of this drop is influenced by the threshold voltage of the
device.  Since the threshold voltage can vary with process
variations, the potential exists for non-uniformity, especially
across large arrays.  This non-uniformity would manifest itself as a
so-called "Fixed Pattern Noise", (FPN).

      Disclosed here is a minor modification to the pixel design that
will alleviate the effect of variations in the characteristics of the
pixel selection transistor.  In this alteration, the pixel selection
transistor is relocated from the output circuit to a...