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Browse Prior Art Database

Sequence Reception Method for a Fibre Channel Protocol Chip

IP.com Disclosure Number: IPCOM000117037D
Original Publication Date: 1995-Dec-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 173K

Publishing Venue

IBM

Related People

Nordstrom, GM: AUTHOR

Abstract

A method is described to distribute the FC-2 sequence reception functions of an ANSI standard Fibre Channel (FC) adapter between a microprocessor and an FC-2 protocol chip, so as to provide good performance at low complexity and cost in the resulting FC-2 protocol hardware.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 31% of the total text.

Sequence Reception Method for a Fibre Channel Protocol Chip

      A method is described to distribute the FC-2 sequence reception
functions of an ANSI standard Fibre Channel (FC) adapter between a
microprocessor and an FC-2 protocol chip, so as to provide good
performance at low complexity and cost in the resulting FC-2 protocol
hardware.

      ANSI Fibre Channel (FC) is a switched fiber optic I/O
interconnect.  The Fibre Channel FC-2 protocol segments transmitted
data into "Frames" and "Sequences" that are related within the
context of an "Exchange", a logical session between two Fibre Channel
ports (N_Ports).  An N_Port receiving data must quickly allocate
resources to newly-initiated, inbound Sequences and Exchanges.  Such
high speed handling of inbound data generally requires hardware
implementations.  However, the FC-2 Frame Headers that contain
Sequence and Exchange identifiers, along with other data description
information, are complex to decode, especially at high rates of data
transfer.  Therefore, a microprocessor implementation of some header
processing functions is desirable to both avoid high complexity in
high-speed hardware implementations.  This leads to a combined
hardware and microprogramming implementation of the FC-2 protocol.
The distribution of FC-2 functions between the microprocessor and
hardware offer many options, and the particular selection of these
options greatly affects cost and performance of the FC-2 protocol
implementation.

      Because Sequence reception is a high-speed event, and Frames
from different Sequences may be multiplexed on the FC link,
expensive, high-speed protocol hardware should be optimized towards
data movement between the FC optical link and the memory served by
the N_Port.  This means that the protocol hardware resources should
be dedicated largely to multiple data channels consisting of
high-bandwidth internal Frame and Sequence reception buffers and
status registers, and possibly pre-allocated buffers in the memory
served by the FC N_Port.

      On the other hand, the functional complexity of Frame Header
parsing is well suited to microprocessor programming, and avoid the
use of expensive high-speed hardware resources for these functions.
Thus, the microprocessor performs such functions as validation of
Frame Header information that is common throughout a received
Sequence, allocation of resources when a sequence is received
containing a new Exchange Id and related parameters, etc..  Provided
that the FC-2 protocol hardware contains multiple data channels,
which can be pre-programmed for unexpected, new Sequences as well as
active, known Sequences, the microprocessor can perform Frame Header
processing concurrent with Sequence data reception with latencies
that do not demand extremely high performance microprocessors.

      Generally, FC-2 protocol events that need high-speed
microprocessor interaction occur at sequence boundaries, and at
points within se...