Browse Prior Art Database

Power Management Clock Change for 603 Processor

IP.com Disclosure Number: IPCOM000117057D
Original Publication Date: 1995-Dec-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 89K

Publishing Venue

IBM

Related People

Lam, SH: AUTHOR [+3]

Abstract

Disclosed is a design to change the PowerPC* 603 clock dynamically for Power Management (PM). The Operating System adjusted the 603 CPU clock according to the system load to reduce the system power consumption. o This invention supports different Power Management (PM) clock modes (Max/Med/Low) based on programming the CPU Clock Control Register (CCCR). o CPU Clock Control Register is used to select CPU clock rate. These register bits feed the Clock Control Buffer (CCC_BUF). The CCC_BUF outputs are logically connected to the 603's PLL_CFG(0:3) pins. The CCCR and CCC_BUF are initialized with the default value during reset. The figure shows the clock change logic and example of different clock configurations.

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Power Management Clock Change for 603 Processor

      Disclosed is a design to change the PowerPC* 603 clock
dynamically for Power Management (PM).  The Operating System adjusted
the 603 CPU clock according to the system load to reduce the system
power consumption.
  o  This invention supports different Power Management (PM) clock
      modes (Max/Med/Low) based on programming the CPU Clock Control
      Register (CCCR).
  o  CPU Clock Control Register is used to select CPU clock rate.
      These register bits feed the Clock Control Buffer (CCC_BUF).
The
      CCC_BUF outputs are logically connected to the 603's
PLL_CFG(0:3)
      pins.  The CCCR and CCC_BUF are initialized with the default
      value during reset.  The figure shows the clock change logic
and
      example of different clock configurations.
  o  Sequence flow to change CPU clock frequency
     -  Program the CPU Clock Control Register in the PMC to select a
         different CPU clock rate.  The new clock rate will be
updated
         when CPU awaked.
     -  Flush CPU cache
     -  Program the 603's SLEEP bit to enter SLEEP mode.
        -  CPU responses with the QREQ  signal.  In our system QACK
            signal of the CPU is tied to QREQ .  CPU will shutdown
            its units within 9 system clocks from the time QACK
            active.
        -  Carrera loads the CCC_BUF after programmable system
            clocks from QREQ  goes active low.  The programmable
            value is defined in the CPU Clock Change Programmable
            Timings Register, CCCPTR.  The default value is 12 system
            clocks.
        -  Carrera generates CC_PMI  (Clock Change PMI) to wake the
            CPU up after CCC_BUF is loaded and an additional stable
            time which allows the Phase Lock Loop (PLL) to relock to
            a new frequency.  Th...