Browse Prior Art Database

Switching the Target Memory

IP.com Disclosure Number: IPCOM000117064D
Original Publication Date: 1995-Dec-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 113K

Publishing Venue

IBM

Related People

Hilgendorf, R: AUTHOR [+3]

Abstract

Fig. 1 shows a computer system, where two I/O adapters are connected via a single bus to dedicated ports on two independent memories. The CPU of the system communicates with the two memories through extra ports. Each memory is able to work on two operations (ODD and EVEN address) simultaneously; each adapter may have two internally pending operations. The target memory for each of the four possible operations is unpredictable in that way that it is independant of any former operation.

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This is the abbreviated version, containing approximately 52% of the total text.

Switching the Target Memory

      Fig. 1 shows a computer system, where two I/O adapters are
connected via a single bus to dedicated ports on two independent
memories.  The CPU of the system communicates with the two memories
through extra ports.  Each memory is able to work on two operations
(ODD and EVEN address) simultaneously; each adapter may have two
internally pending operations.  The target memory for each of the
four possible operations is unpredictable in that way that it is
independant of any former operation.

      To start an operation the bus has to be requested first.  Once
it is granted, the operation has to be performed according to the
protocol of the bus.  For a memory-read operation, the memory will
send data back to the requestor after a varying delay, where min.
and max.  of the delay is known but not the actual delay.  It is not
possible to defer the transfer of data by an external line.

      If there would be only one adapter or one memory in the system,
it would not be difficult to handle the data transfers.  However,
problems arise if each of the adapter requests an operation for a
different memory.  The case may exist where both memories try to
transfer data for a memory-read operation at the same time, thus
providing wrong data to the requestors.  Therefore, a mechanism must
be put in place to ensure that only operations to the same memory can
be initiated.  Only after they are finished, operations for the other
memory may be requested and executed.

      To enforce that both adapters always work with the same memory
at a given time, a specific communication between the adapters will
be established.  Fig. 2 shows that part of the logic which selects
the target memory and allows to switch the target memory.  As the
circuitry is identical in both adapter, switching will be done
synchronous.

      Assuming the current setting of the circuitry is such that both
adapter work with Memory_0; Zero_Select and Zero_Select_DLY are both
active.  Now in Adapter_1 an EVN_MEM1_REQ signal becomes active on
OR-gate 1.  Following this, AND_OR-gate2 will become active, too.  At
the next system-clock latches 3 and 4 are set.  While the output of
latch 3 is direct fed to lat...