Browse Prior Art Database

Unit Level Testcase Generator

IP.com Disclosure Number: IPCOM000117065D
Original Publication Date: 1995-Dec-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Jaisimha, N: AUTHOR [+2]

Abstract

Disclosed is a tool which generates test cases automatically at the unit level using the system simulation results as its input. The unit level model is usually smaller in size compared to the system model and therefore it takes less time to build the model and execute the test case. This tool eliminates the most time consuming steps from system simulation, thereby decreasing the time to debug and verify bug fixes.

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Unit Level Testcase Generator

      Disclosed is a tool which generates test cases automatically at
the unit level using the system simulation results as its input.  The
unit level model is usually smaller in size compared to the system
model and therefore it takes less time to build the model and execute
the test case.  This tool eliminates the most time consuming steps
from system simulation, thereby decreasing the time to debug and
verify bug fixes.

      The Unit Level Testcase Generation tool uses the system
simulation results All Event Trace (AET) and a list of the signals as
inputs.  The list of signals usually contains those signals that need
to be asserted, typically inputs t the design and is provided by the
Logic Designer.  The tool parses through the AET to find if any of
the signals in the list are asserted and if they are, adds them to
the test case.  During simulation, signals will be asserted at
appropriate simulation cycle based on the testcase generated usig the
simulator interface.

      A unit can either be just a small piece of logic or a chip.
The boundary of the unit is usually defined by the list of signals.

      The following example is a test case for a cache.  The tool
looks at certain signals at the beginning of simulation to find the
state and configuration of the cache (as in lines 1 and 2 of example
1).  At cycle 13, it asserts signal "interleave", at cycle 14 the
tool assers signals "address_valid", at cycle 14 the...