Browse Prior Art Database

High Speed Detection of Signals from Digital Magnetic Recording Devices

IP.com Disclosure Number: IPCOM000117072D
Original Publication Date: 1995-Dec-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 95K

Publishing Venue

IBM

Related People

Sands, NP: AUTHOR [+2]

Abstract

Disclosed is a design which employs a receiver architecture, in which the gain and timing recovery are accomplished with local feedback loops. This allows more processing delay in some of the receiver functions, thus reducing power consumption and/or allowing higher operating rate. The receiver incorporates a discrete-time analog equalizer, nonlinear spectral-line timing recovery, automatic gain control, and a novel delay-lock-loop to perform equalization and clock recovery for input to a digital detection algorithm such as Partial-Response Maximum Likelihood (PRML). Another key element of the design is the cascaded phase-locked loop (PLL) for clock recovery and the delay loop to adjust the sampling phase for optical detector performance. The use of cascaded structure allows the two loops to be optimized separately.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

High Speed Detection of Signals from Digital Magnetic Recording Devices

      Disclosed is a design which employs a receiver architecture, in
which the gain and timing recovery are accomplished with local
feedback loops.  This allows more processing delay in some of the
receiver functions, thus reducing power consumption and/or allowing
higher operating rate.  The receiver incorporates a discrete-time
analog equalizer, nonlinear spectral-line timing recovery, automatic
gain control, and a novel delay-lock-loop to perform equalization and
clock recovery for input to a digital detection algorithm such as
Partial-Response Maximum Likelihood (PRML).  Another key element of
the design is the cascaded phase-locked loop (PLL) for clock recovery
and the delay loop to adjust the sampling phase for optical detector
performance.  The use of cascaded structure allows the two loops to
be optimized separately.

      The complete system is shown in Fig. 1 where the read signal
from the pre-amplifier is fed to a gain control system (VGA) for
normalization.  The normalized signal is then passed to the
feedforward timing recovery subsystem, which regenerates the system
clock, and after anti-alias filtering to the sample/hold circuit,
which supplies samples to the discrete-time equalizer.  The equalized
signal is then quantized and passed to the Maximum Likelihood
Sequence Detector (MLSD) using the Viterbi Algorithm (VA), from which
emerges the detected data sequence.  Figure 2.  Feedforward Timing
Recovery Block Diagram

      Fig. 2 shows the elements of the timing recovery subsystem,
which uses the nonlinear spectral line method to extract the symbol
rate clock from the received waveform.  The read signal is first
filtered using a low-Q filter (Q=1) with center frequency at 0.25 the
symbol rate, then fed to a nonlinear element such as a full-wave
rectifier or fourth power device which recreates a tone at the symbol
rate.  It is this tone at the symbol rate which is used to con...