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Protect Diode Scheme for Chips Requiring Isolated Power/Ground Planes for Internal/External Noise Isolation

IP.com Disclosure Number: IPCOM000117081D
Original Publication Date: 1995-Dec-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 155K

Publishing Venue

IBM

Related People

Correale Jr, A: AUTHOR

Abstract

Electro-Static Discharge (ESD) protection schemes require that diodes be connected between each chip pad/pin and the circuit's power supplies. In addition, diodes are required between each power/ground plane employed in the design. Typically, a diode is connected such that it is reversed biased during normal operation, but becomes forward biased and conductive to provide a shunt path for ESD. When individual power and ground planes are employed for internal noise isolation between internal sections of the design (analog, digital) and I/O sections, then protection must be employed to each of the circuits power and grounds, and between each power plane and ground. This is further exasperated when mixed voltage interfaces are involved.

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Protect Diode Scheme for Chips Requiring Isolated Power/Ground Planes
for Internal/External Noise Isolation

      Electro-Static Discharge (ESD) protection schemes require that
diodes be connected between each chip pad/pin and the circuit's power
supplies.  In addition, diodes are required between each power/ground
plane employed in the design.  Typically, a diode is connected such
that it is reversed biased during normal operation, but becomes
forward biased and conductive to provide a shunt path for ESD.  When
individual power and ground planes are employed for internal noise
isolation between internal sections of the design (analog, digital)
and I/O sections, then protection must be employed to each of the
circuits power and grounds, and between each power plane and ground.
This is further exasperated when mixed voltage interfaces are
involved.  The following illustrates a simple, area-effective
technique wherein a single diode stack can be employed to address
both the mixed power supply and multiple power plane ESD problem.

      A typical input pin and associated protect diode configuration
for a single voltage interface and a single power/ground plane is
illustrated in Fig. 1.  The ESD protection is comprised of a pair of
diodes:  one connected between the input pin and ground, the other
connected between the input pin and the 3-volt supply.  The diode
connected to ground provides a shunt path for negative ESD pulses,
while the one connected to the 3-volt supply provides a shunt path
for positive ESD pulses.  For mixed power supply interfacing, a
single diode to Vdd is not adequate if the interface potential is
greater than the internal chip supply.  For these cases, a diode
stack configuration must be employed.  A scheme that efficiently
handles the diode stack for mixed supply interfacing employing a
single internal power supply and ground was reported in the [*]  In
that disclosure, it was shown that an internal power plane, Vdp, was
employed wherein a single diode was connected between it and the
input pad/pin.  This Vdp internal plane was brought out to a separate
chip pin which was biased to the highest potential in the system
requiring interfacing.  This is illustrated in Fig. 2.  The power
supply pin, Vdd, would also have a diode connected to the Vdp plane
and one to ground.

      As seen in the following bulletin, the need for a separate
diode bias supply pin has been eliminated and the approach addresses
the complications associated with multiple isolated internal
supplies.

      Fig. 3 illustrates the use of a multiple diode stack to provide
conductivity between Vdp and Vdd.  In this figure, four (4) diodes
are employed to allow interfacing the chip I/O with that of a higher
supply (5V).  Hence, a total of five (5) diodes are used between the
various chip I/O's and the internal supply, Vdd.  This arrangement
allows for the input potential to be five diode drops higher than the
internal sup...