Browse Prior Art Database

PCI Type 1 Configuration in Type 0 Only Systems

IP.com Disclosure Number: IPCOM000117111D
Original Publication Date: 1995-Dec-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 6 page(s) / 254K

Publishing Venue

IBM

Related People

Doidge, DA: AUTHOR [+4]

Abstract

A limitation is known to exist in some PCI bus controllers, in which the controller is not capable of implementing type 1 configuration cycles. This puts a limitation on the systems that are designed with such controllers. These systems will not be capable of using PCI to PCI bridges to implement multiple busses in the system, since no type 1 configuration cycles can be generated to initialize devices on the other side of these bridge chips. The invention presented in this disclosure allows a modified type 0 configuration cycle to be converted to a type 1 configuration cycle. This will allow the use of PCI to PCI bridge chips and multiple busses in systems where the PCI bus controller is not capable of generating a type 1 configuration cycle.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 25% of the total text.

PCI Type 1 Configuration in Type 0 Only Systems

      A limitation is known to exist in some PCI bus controllers, in
which the controller is not capable of implementing type 1
configuration cycles.  This puts a limitation on the systems that are
designed with such controllers.  These systems will not be capable of
using PCI to PCI bridges to implement multiple busses in the system,
since no type 1 configuration cycles can be generated to initialize
devices on the other side of these bridge chips.  The invention
presented in this disclosure allows a modified type 0 configuration
cycle to be converted to a type 1 configuration cycle.  This will
allow the use of PCI to PCI bridge chips and multiple busses in
systems where the PCI bus controller is not capable of generating a
type 1 configuration cycle.

      One of the advantages of the PCI bus architecture is its
ability to support multiple PCI busses in a single system.  This is
illustrated in Fig. 1.  This Figure shows two potential PCI bus
configurations.  The single bus configuration illustrates a common
architecture, where a microprocessor subsystem, and some number of
other devices share access to a single PCI bus.  The multi bus
configuration illustrates how a system could be implemented using a
hierarchy of PCI busses.  This hierarchy is made up of a primary PCI
bus, and some number of secondary PCI busses.  Here, a microprocessor
subsystem, and some number of devices share access to the primary PCI
bus.  Additionally, some number of secondary PCI busses with PCI
devices sharing access to each bus can also exist in the system.  In
a multiple bus system, inter-bus access is controlled by devices
known as PCI to PCI bridges.  These bridges provide two important
functions for the system:
  1.  For bus accesses where the source and destination devices are
on
       the same bus, do not forward the access to any other PCI bus
in
       the system.
  2.  For bus accesses where the source and destination devices are
on
       different busses, forward the access from the source bus to
the
       appropriate destination bus.

      One of the types of bus accesses that is of interest in a PCI
system is the configuration cycle.  The PCI architecture requires
that all PCI devices have a set of common registers known as
configuration registers.  These registers contain setup information
for each device such as its position in the address space, and device
enable functions.  For PCI to PCI bridges, these registers also
include information about which busses are on which side of the
bridge, and the address range of memory and I/O cycles that should be
forwarded to other busses.

      There are two types of configuration cycles defined by the PCI
architecture.  These are known as type 0 and type 1 configuration
cycles.  A type 0 configuration cycle is used to access the
configuration registers of a device that exists on the same bus tha...