Browse Prior Art Database

High-Density Flip-Chip Packaging Technique

IP.com Disclosure Number: IPCOM000117134D
Original Publication Date: 1995-Dec-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 105K

Publishing Venue

IBM

Related People

Durham, CM: AUTHOR [+2]

Abstract

In an effort to increase the density and performance of VLSI, Engineers strive to not only design the best possible chips, but also the best possible packaging and systems. This has resulted in faster and more complex systems. The invention described in this disclosure describes a new packaging technique that is an extension of existing technology and provides increased density and performance.

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High-Density Flip-Chip Packaging Technique

      In an effort to increase the density and performance of VLSI,
Engineers strive to not only design the best possible chips, but also
the best possible packaging and systems.  This has resulted in faster
and more complex systems.  The invention described in this disclosure
describes a new packaging technique that is an extension of existing
technology and provides increased density and performance.

      VLSI chips have long been packaged using "flip-chip" technology
to increase density over previously used "wire-bond" technology.  A
diagram of this technique is shown in Fig. 1.  It has resulted in
higher density packaging and an increased number of interconnects
(input and output signals) over wire-bond techniques.

      Extensions to flip-chip packaging have been done where multiple
chips are packaged on a single package in an array pattern as shown
in Fig. 2.  This technique has provided even further density
improvements over the single-chip package of Fig. 1.

      However, note that interconnects between two chips must go from
the first chip, through the multi-chip package, and then to the
second chip.  This may (and has in some cases) become the limiting
factor in the subsystem performance of such packages.  That is,
signals (busses) have been forced to run at reduced speeds (often 3:2
or more ratios of the chip clock).

      A new packaging technique proposal is described here that
reduces the interconnect distance, providing a higher-speed
connection between multiple chips.  This permits 1:1 clock ratios,
increase overall performance.  It  uses the flip-chip packaging
technique to interconnect two (or more) VLSI chips, then using
flip-chip packaging again to connect this structure to a special
package.  This shown in Fig. 3.  Additionally, the diagram of Fig. 3
may be extended to multiple chips interconnecting to ch...