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Field Effect Transistor Ohmic Short Protection

IP.com Disclosure Number: IPCOM000117174D
Original Publication Date: 1996-Jan-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Narita, I: AUTHOR

Abstract

Disclosed is the protection mechanism for the Field Effect Transistor (FET) ohmic short. When the FET gets the state of the ohmic short, the source-drain resistance of the FET becomes higher to some ohms. If the FET is in the power line, it gets heat and sometimes it is consumed. In this invention, the state of the ohmic short is monitored by the measuring of the voltage value between the source and the drain of the FET. When the ohmic short condition is detected, the protection mechanism stops the current flow in the FET and keeps the FET from overheating. With this invention, the ohmic short condition is detected sooner than other methods which monitor the heat emission of the FET. Because the voltage is monitored in this invention, the FET can be kept from overheating.

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Field Effect Transistor Ohmic Short Protection

      Disclosed is the protection mechanism for the Field Effect
Transistor (FET) ohmic short.  When the FET gets the state of the
ohmic short, the source-drain resistance of the FET becomes higher to
some ohms.  If the FET is in the power line, it gets heat and
sometimes it is consumed.  In this invention, the state of the ohmic
short is monitored by the measuring of the voltage value between the
source and the drain of the FET.  When the ohmic short condition is
detected, the protection mechanism stops the current flow in the FET
and keeps the FET from overheating.  With this invention, the ohmic
short condition is detected sooner than other methods which monitor
the heat emission of the FET.  Because the voltage is monitored in
this invention, the FET can be kept from overheating.

      The Figure shows the circuit of the invention.  The Figure
shows the battery charging circuit in the Notebook PC.  In the
Figure, SW1, SW2, and SW3 are the Nch FETs.  They become ON when the
charge pump circuit supplies high voltage to their gates through D1,
D2, and D3.  The one chip microcomputer monitors the voltage value of
the point of V1 and V2.  Assume that the charging current I3 is 3A
and the total resistance of SW1, SW2 and SW3 is 0.1 ohm in the
Figure.  Also, assume that I2 is nearly equal to 0A (power off or
suspend mode) and I1 is nearly equal to I3 for the simplicity.  In
the normal condition, the voltage d...