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Dynamically Improving 604 Cache Utilization in an Multi-Processor Environment

IP.com Disclosure Number: IPCOM000117193D
Original Publication Date: 1996-Jan-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Heisch, RR: AUTHOR

Abstract

Cache cross invalidates (conflict misses due to coherency for heavily shared variables) in an MP environment have been shown (by BUll/others) to be a major cause of decreased MP performance. Constant frequent access to OS semaphores (for locking/exclusive access/etc.) by multiple uP's causes constant cache flushing to maintain cache coherency.

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Dynamically Improving 604 Cache Utilization in an Multi-Processor
Environment

      Cache cross invalidates (conflict misses due to coherency for
heavily shared variables) in an MP environment have been shown (by
BUll/others) to be a major cause of decreased MP performance.
Constant frequent access to OS semaphores (for locking/exclusive
access/etc.) by multiple uP's causes constant cache flushing to
maintain cache coherency.

      The solution presented here utilizes the 604's built in
performance monitor capabilities and the 604's cache write policy
programability together to provide an adaptive, dynamically updated
cache write policy on a per processor basis.  Each processor
similarly programs its performance monitor to sampled cache misses
(and collect reference effective address info) as well as lateral L2
intervention miss data.  At some periodic interval, the sample data
is analyzed and correlated to known shared variable address locations
to determine which shared data is causing high miss rates (due to
cross invalidates).  The cache write policy is then modified (changed
to write through vs. writeback for the most common case) for each
specific shared variable independently on each processor to attempt
to achieve overall system performance improvement.