Browse Prior Art Database

Chipset Low Power Mode while Maintaining DRAM Refresh

IP.com Disclosure Number: IPCOM000117208D
Original Publication Date: 1996-Jan-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Drerup, BC: AUTHOR [+2]

Abstract

Disclosed is a method for a chipset which contains a DRAM memory controller to enter a low power state while continuing to refresh DRAM memory. This method allows a secondary clock input signal to be used to generate refresh while the primary clock input is stopped during the low power state. This method also allows the secondary clock to be changed to a different frequency during normal operation (not low power mode) so that it can also be used as a clock input for a purpose other than refresh.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Chipset Low Power Mode while Maintaining DRAM Refresh

      Disclosed is a method for a chipset which contains a DRAM
memory controller to enter a low power state while continuing to
refresh DRAM memory.  This method allows a secondary clock input
signal to be used to generate refresh while the primary clock input
is stopped during the low power state.  This method also allows the
secondary clock to be changed to a different frequency during normal
operation (not low power mode) so that it can also be used as a clock
input for a purpose other than refresh.

      To minimize power consumption within the chipset, the primary
clock is stopped during the low power mode.  Since the chipset
contains a memory controller, the logic which refreshes memory must
continue to be clocked by a secondary clock during the low power
mode.  Only the logic required for refreshing the DRAM is clocked by
the secondary clock input.

      In addition to the memory controller, the chipset contains a
PCI bus interface.  During normal operation the secondary clock is
used as a reference clock for the PCI bus.  This reference clock is
required because the PCI bus is run at a different (slower) clock
frequency than the primary clock.

      The frequency of the secondary clock must match the frequency
of the PCI bus during normal operation.  However, to provide maximum
power savings, the secondary clock is allowed to run slower while in
low power mode (note that the PCI bus is idle during this period).

      The block diagram below shows the logic requir...