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Browse Prior Art Database

Power-Managing the PowerPC 601* CPU

IP.com Disclosure Number: IPCOM000117227D
Original Publication Date: 1996-Jan-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 159K

Publishing Venue

IBM

Related People

Appel, WD: AUTHOR [+5]

Abstract

A significant portion of the power consumed by a computer is dedicated to the CPU. The quiescent power consumption of the PowerPC 601* and PowerPC 601ev CPUs (601) is low compared to the dynamic power consumption, which is directly proportional to the operating clock frequency. This application note presents a high level discussion of implementing 601 power management by soft stopping the 601 and then stopping the 601 PCLK_EN#. A hardware and software algorithm is described which allows automatic reduction of power during periods when the CPU is not in use. The methods described herein are suitable for both the 601 and 601ev processors.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Power-Managing the PowerPC 601* CPU

      A significant portion of the power consumed by a computer is
dedicated to the CPU.  The quiescent power consumption of the PowerPC
601* and PowerPC 601ev CPUs (601) is low compared to the dynamic
power consumption, which is directly proportional to the operating
clock frequency.  This application note presents a high level
discussion of implementing 601 power management by soft stopping the
601 and then stopping the 601 PCLK_EN#.  A hardware and software
algorithm is described which allows automatic reduction of power
during periods when the CPU is not in use.  The methods described
herein are suitable for both the 601 and 601ev processors.

      Table 1 shows the measured typical power consumption of the
601ev in a power-managed system while running and while PCLK_EN# is
stopped.  The system supplies VddI/O = 5v and VddINT = 2.7v.
Processor speed is 120MHz and bus speed is 60MHz (Table 1).

      The major hardware blocks involved in power management are
shown in Fig. 1.  The power management controller (PMC) controls the
various power management components.  The PMC function can be
implemented by a combination of devices.  The clock control logic
(CCL) contains control registers and a serial interface to the MPC970
clock generator.  The MPC970 stops and restarts PCLK_EN# in an
orderly manner in response to commands received via the serial
interface.

      The general algorithm for putting the 601 into low power mode
is shown in Fig. 2.  Once the operating system (OS) detects a system
idle condition, it (if required) instructs all of the CPU and PCI bus
agents not to access system memory until further notice, but to issue
an interrupt if a system memory access is required.

      The OS then executes the 601 soft stop algorithm, during which
it asserts QUIESC_REQ.  The PMC then asserts SYS_QUIESC#, causing the
601 to enter the soft stop state.  At the same time, the PMC asserts
FREEZE# to the CCL, and the CCL sends the freeze command to the clock
generator over a serial link.  The clock generator then stops
PCLK_EN# to the 601.  At this point the 601 is in low power mode.

Soft Stopping the 601

      A soft stop allows all outstanding instructions and bus
transfers to complete.  The OS initiates a soft stop by executing the
series of instructions shown in Table 2.  This sequence flushes CPU
bus buffers, synchronizes the CPU bus agents, and causes the 601 to
assert QUIESC_REQ.  In response to QUIESC_REQ, the PMC quiesces all
required system activity in an orderly manner.  This allows the
system to complete any activities that might otherwise be adversely
affected by stopping the CPU clock.  The PMC then asserts SYS_QUIESC#
to the 601.

      On receipt of SYS_QUI...