Browse Prior Art Database

Using Multiple Preallocated Pools of Memory for Bi-Endian Systems

IP.com Disclosure Number: IPCOM000117242D
Original Publication Date: 1996-Jan-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Byrn, JW: AUTHOR [+4]

Abstract

A method for supporting zero copy communication interfaces in a multiple byte ordered computing system is disclosed. These systems are sometimes referred to as bi-endian systems. The scheme disclosed uses a byte-order translating bridge, whose byte operations are controlled by the memory address presented to the bus. Multiple pools of memory descriptors are maintained by the communication device. When the communication device prepares a data transfer of received data, it chooses a descriptor from the pool of memory descriptors appropriate for the particular application or communication channel. Using that pool of descriptors, the communications adapter can transfer data in such a way as to cause the bridge to perform the appropriate swapping and reflecting operations on the data as it is transferred.

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This is the abbreviated version, containing approximately 52% of the total text.

Using Multiple Preallocated Pools of Memory for Bi-Endian Systems

      A method for supporting zero copy communication interfaces in a
multiple byte ordered computing system is disclosed.  These systems
are sometimes referred to as bi-endian systems.  The scheme disclosed
uses a byte-order translating bridge, whose byte operations are
controlled by the memory address presented to the bus.  Multiple
pools of memory descriptors are maintained by the communication
device.  When the communication device prepares a data transfer of
received data, it chooses a descriptor from the pool of memory
descriptors appropriate for the particular application or
communication channel.  Using that pool of descriptors, the
communications adapter can transfer data in such a way as to cause
the bridge to perform the appropriate swapping and reflecting
operations on the data as it is transferred.

      In this solution, the bridge chip which provides memory cycle
connectivity from the I/O adapter to the host memory has an address
re-mapping and protection capability.  As part of this capability, a
given address range will have an endian and byte reflection
association so that a reference by the I/O adapter to the host memory
will be transformed (address swapping and byte swapping and
reflecting appropriate to the memory space).  While there are a
number of ways to communicate the byte ordering information to the
bridge chip, the scheme which uses Translation Control Entries (TCE...