Browse Prior Art Database

High Bandwidth, Low Latency Interconnection Network for Information Transfer

IP.com Disclosure Number: IPCOM000117256D
Original Publication Date: 1996-Jan-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 6 page(s) / 196K

Publishing Venue

IBM

Related People

Deshpande, S: AUTHOR [+7]

Abstract

Disclosed is a synchronous high speed Interconnection Network (ICN) that can be used to transfer information at low latency and high bandwidth. It can be used in a multiprocess or containing multiple processors, memories and I/O devices, for example, where it can be utilized to transfer: 1. Memory and I/O requests 2. Memory and I/O responses, such as data and acknowledgements 3. Cache coherence request and response transactions among processors and memories 4. Interrupt transactions and their responses

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 39% of the total text.

High Bandwidth, Low Latency Interconnection Network for Information
Transfer

      Disclosed is a synchronous high speed Interconnection Network
(ICN) that can be used to transfer information at low latency and
high bandwidth.  It can be used in a multiprocess or containing
multiple processors, memories and I/O devices, for example, where it
can be utilized to transfer:
  1.  Memory and I/O requests
  2.  Memory and I/O responses, such as data and acknowledgements
  3.  Cache coherence request and response transactions among
       processors and memories
  4.  Interrupt transactions and their responses

The following features characterize the ICN:
  1.  The ICN embodies one or more independent bidirectional data
       paths which each carry a specific type of information.
  2.  A transaction is a unit of information sent from a source to a
       destination
  3.  A transaction can occupy one or more of the data paths for one
or
       more clock cycles.  The time a tranaction occupies each of its
       selected data paths is fixed and predetermined.  This results
in
       a transaction format defined over data paths and time.
  4.  In addition, transactions may have priorities such that high
       priority transaction may bypass low priority ones.
  5.  The ICN is in the form of a single stage crossbar defined over
       each data path.  Each such crossbar has idenical number of
ports.
  6.  The crossbar is sliced, meaning, the data path is partitioned
       bit-wise.  Each partition is called a slice.  The individual
data
       paths are implemented by aggregating slices.  This way the
width
       of a data path is made scalable.
  7.  A chip may contain only an integral number of slices
  8.  The crossbar are designed such that effective number of ports
       is programmable.
  9.  Each port of the ICN may be connected to a communicating entity
       such as a processor or memory.
 10.  The entity or the crossbar port signals the desire to transmit
       a transaction via unidirectional signals
 11.  The same signals are also used to identify the format of the
       transaction.
 12.  The crossbars may be implemented internally to the chip either
       as single- or multi-stage pipeline
 13.  Multiple transactions may be in flight at the same time at any
       given port as long as they do not have conflicting formats.
 14.  The transactions can be rejected by the recipient.  A rejected
       transaction is signalled via unidirectional control lines.
The
       sending entity my subsequently reattempt to send the rejected
       transaction.
 15.  The recipient alternatively control the flow of transactions to
       it via a Backpressure signal sent over a unidirectional line.

Fig. 1 illustrates a system built using a RAMJET-specific
implementation o...