Browse Prior Art Database

Interface for Pattern Skipping Built-in Self-Test

IP.com Disclosure Number: IPCOM000117257D
Original Publication Date: 1996-Jan-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Douskey, SM: AUTHOR [+2]

Abstract

Described is an interface for Pattern Skipping Built-In Self-Test (PSBIST) at a manufacturing tester. It is a simple version that will become a standard for testing many parts.

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Interface for Pattern Skipping Built-in Self-Test

      Described is an interface for Pattern Skipping Built-In
Self-Test (PSBIST) at a manufacturing tester.  It is a simple version
that will become a standard for testing many parts.

      Pattern skipping is used to reduce test time without coverage
loss.  This is accomplished by eliminating unproductive tests.

      For PSBIST, a shadow Pseudo-Random Pattern Generator (PRPG) is
used to store the starting value for each test.  Since IOs are at a
premium, the internal shadow PRPG is copied from the PRPG at a
specified time during the scan initialization of the current test
sequence.  A skip counter determines when the shadow PRPG is loaded.
The skip counter is loaded from IO pins at certain stages of the
test.  It's value was determined previously by fault analysis tools.
The largest possible skip value is the channel length used when scan
initializing from the PRPG.

      Fig. 1 shows a typical internal hardware configuration for
PSBIST.  Note that the MUXes allow internal testing with a standard
skip value of '0001'.

Fig. 2: Timings of tester driven PSBIST Stepping through Fig. 2, the
timing sequence for this interface:
  1.  The chip is initialized with a scan
  2.  The skip count is driven to the IO
  3.  The GO signal triggers the start of a test loop
  4.  The GO signal is synchronized and signals a load of the PRPG
       and skip counter
  5.  One cycle later the scan of the...