Browse Prior Art Database

Method to Arbitrate for an Interfering Operation

IP.com Disclosure Number: IPCOM000117277D
Original Publication Date: 1996-Jan-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 81K

Publishing Venue

IBM

Related People

Hilgendorf, R: AUTHOR [+2]

Abstract

In a computer system where the memory is separated into two or more parts, each accessible via its own protocol-controlled bus, and where these busses are interconnected by at least two basically identical bus adaptors, a method for avoiding deadlock is proposed which provides a specific communication between the adaptors wherein one adaptor asks the other if the common bus being used.

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This is the abbreviated version, containing approximately 53% of the total text.

Method to Arbitrate for an Interfering Operation

      In a computer system where the memory is separated into two or
more parts, each accessible via its own protocol-controlled bus, and
where these busses are interconnected by at least two basically
identical bus adaptors, a method for avoiding deadlock is proposed
which provides a specific communication between the adaptors wherein
one adaptor asks the other if the common bus being used.

      In (*) a corresponding method for interconnecting such
separate busses by one bus adaptor is disclosed.  Separation of
memory content is accomplished such that the first 512 bytes are
located in MEM-1, the second in MEM-2, the third 512 bytes again in
MEM-1 and so on.

      The proposed two-memory bus system employs two bus adaptors as
depicted in Fig. 1, to enable the I/O to access the entire memory.
For the proposed solution, some communication between adaptor 1 and
adaptor 2 is introduced.  Basically adaptor 1 asks via a request line
if the window is open.  Via a grant line adaptor 2 tells adaptor 1 if
it may use Bus 3 for the interfering operation and that it will keep
the window open until the request is taken away.

      Fig. 2 shows the hardware involved in this handshake.  An
interfering operation (Sense/Control from Pu to IBU) tries to achieve
control on bus 3 via ADAPTOR (1).  It, therefore, sets latch LT1.
The output of LT1 is fed to AND-gate (2) DATA_AVAILable to produce
START_DATA_TRANSFER.  Sec...