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Browse Prior Art Database

Flush Reset Circuit

IP.com Disclosure Number: IPCOM000117288D
Original Publication Date: 1996-Jan-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Yasuda, T: AUTHOR

Abstract

Disclosed is a circuit for resetting latches with scan path. Clock gating is a common method for power saving while it is not so simple to reset latches of which the clock is gated by some signals. This circuit enables reset on such kind of latches: 1. without using latch with asynhronous reset input, 2. before clock starting the correct performance or recovering from the power down mode and 3. regardless of internal state of the power save circuit.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 70% of the total text.

Flush Reset Circuit

      Disclosed is a circuit for resetting latches with scan path.
Clock gating is a common method for power saving while it is not so
simple to reset latches of which the clock is gated by some signals.
This circuit enables reset on such kind of latches:
  1.  without using latch with asynhronous reset input,
  2.  before clock starting the correct performance or recovering
from
       the power down mode and
  3.  regardless of internal state of the power save circuit.

      Fig. 1 shows the flush reset circuit for level sensitive type
two phase latch.  Additional gates are (A), (B), (C) and (D).
(Replacing the gate (B) by OR gate changes circuit for preset.)  The
output of this latch becomes "0" when either Power On Reset (-POR) or
ENABLE becomes low.  That is, this circuit resets the latch as soon
as the chip goes into initial or power down mode.  Moreover, this
reset is independent of internal state of the power save circuit and
occurs surely even after stopping of B and C CLOCK.  The additional
gates are necessary for limited latches which require reset at
initial or recovery from power down.  So it doesn't cause so much
increase of hardware.  Fig. 2 shows how to implement the same idea
for scan multiplex type two phase latch.  For this latch, additional
gates are from (A) to (E).  In both of the circuits the output of the
gate (A) can flush L1 and L2 at the same time.  Therefore, these
circuits complete reset right a...