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Browse Prior Art Database

No-Overlap-Current CMOS Driver/Buffer/Inverter Circuit

IP.com Disclosure Number: IPCOM000117303D
Original Publication Date: 1996-Jan-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 83K

Publishing Venue

IBM

Related People

Miyatake, H: AUTHOR [+2]

Abstract

Disclosed are CMOS no-overlap-current driver, buffer, and inverter circuits. Because of their logical operation, the circuits have no overlap currents even at their output state transitions.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

No-Overlap-Current CMOS Driver/Buffer/Inverter Circuit

      Disclosed are CMOS no-overlap-current driver, buffer, and
inverter circuits.  Because of their logical operation, the circuits
have no overlap currents even at their output state transitions.

      The circuits comprise an output or driving stage and a
pre-driver stage.  The output stage consists of a p-channel MOS
transistor as a pull-up device and a n-channel MOS transistor as a
pull-down device.  The pre-driver controls the gate nodes of the
p-channel and the n-channel MOS transistors of the output stage.

      The point is that the pre-driver controls the gate nodes of the
output stage transistors in the way that the both transistors cannot
turn on at the same time during the state transition period.

      Fig. 1 shows one of the proposed buffer or driver circuits.
OUT is the output of this circuit and IN is the input.  Signals on
NET1 and NET2 are the inverse of the signals GP and GN, respectively,
which control the transistors of the output stage.  Both output stage
transistors do not turn on at the same time:  namely, when the
circuit makes the state transition, starting from the state that one
of the output stage transistors is on, it goes into the state that
both of them are off, and then to the sate that the other one of the
transistors is on.  This sequence is assured through the logical
operation by the pre-driver logic gates which have as their inputs
the signals from the output stage control signals, GP and GN.  Shown
in Fig. 2 is an example of the buffer or driver circuit with an
output enabling control, EN....