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Spec-Passing: An Approach to System-Level Static Timing Analysis

IP.com Disclosure Number: IPCOM000117318D
Original Publication Date: 1996-Feb-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 193K

Publishing Venue

IBM

Related People

Fredrickson, MS: AUTHOR [+2]

Abstract

Disclosed is an algorithm in which a non-hierarchical static timing analysis program can be used to analyze the timing of complex electronic systems which are described by a hierarchical logical model (net-list). The idea is to use the timing analysis program separately on each level of the hierarchical logic model, passing between these analysis levels the necessary information to establish the bounds of the timing behavior of the system.

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Spec-Passing:  An Approach to System-Level Static Timing Analysis

      Disclosed is an algorithm in which a non-hierarchical static
timing analysis program can be used to analyze the timing of complex
electronic systems which are described by a hierarchical logical
model (net-list).  The idea is to use the timing analysis program
separately on each level of the hierarchical logic model, passing
between these analysis levels the necessary information to establish
the bounds of the timing behavior of the system.

      The theory and practice of static timing analysis is well
developed for non-hierarchical logic models (1 - 3), and will not be
described in detail in this paper.  The object of static timing
analysis is to quickly ascertain whether or not any potential timing
problems exist in an electronic design.  This is done by propagating
the latest possible signals through the slowest paths in the logic
and testing those signals at critical points to see whether or not
they are too late for proper operation of the circuit.  Similarly,
the earliest possible signals are propagated through the fastest
logic paths and are tested to see if they are too early for proper
circuit operation.  The basic premise of static timing analysis can
be stated as follows: "If the slowest signal is not too slow, none
of the signals are too slow, and, if the fastest signal is not too
fast, none of the signals are too fast."  Analyzing the slowest and
fastest signals allows the analysis to bound the timing behavior of
the circuit without having to analyze all of the multitudes of
possible timing relationships in the design.

      Static timing analysis is typically run on a non-hierarchical
logic model which represents an electronic chip or a piece of a chip.
The model consists of blocks (which represent logical circuits) and
nets (which represent connections between the circuits).  The latest
and earliest signals are propagated through the blocks and nets.
Both blocks and nets delay the signals as the signals are propagated.
Signal arrival-times are tested at storage elements, logic outputs,
and other critical locations to make sure that the circuit timing
constraints are met.

      To analyze the timing of systems which contain multiple chips,
one approach which is used today is that each chip is analyzed
separately, and the person performing the analysis takes the earliest
and latest signal arrival-times on the chip outputs, adds
system-level wire delays to those arrival-times and passes these new
arrival-times to the inputs of chips which are fed by those signals.
For example, as simple system may consist of chip A and chip B and a
connection going from chip A to chip B.  In this case, the designer
would analyze chip A, get the earliest and latest possible
arrival-times on the output of chip A, add the wire delay between A
and B, and use these arrival-times as input-arrival-times when chip B
is analyzed.  This is called passing t...