Browse Prior Art Database

External Address Match Interface for Network Controller Chips

IP.com Disclosure Number: IPCOM000117331D
Original Publication Date: 1996-Feb-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 200K

Publishing Venue

IBM

Related People

Lee, JK: AUTHOR [+4]

Abstract

Disclosed is an "External Address Match Interface" which allows a network controller chip's Address Match function to be extended through external logic. It minimizes the cost and complexity of the base network controller chip while allowing its Address Match function to be expanded as needed for advanced applications like bridging, routing and switching.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 26% of the total text.

External Address Match Interface for Network Controller Chips

      Disclosed is an "External Address Match Interface" which allows
a network controller chip's Address Match function to be extended
through external logic.  It minimizes the cost and complexity of the
base network controller chip while allowing its Address Match
function to be expanded as needed for advanced applications like
bridging, routing and switching.

      The External Address Match Interface consists of six I/O pins
on the network controller chip.  Application specific logic can be
designed and connected to these six I/O pins to expand the network
controller chip's Address Match function.  The six pin interface
provides all the handshaking necessary to allow complex Address Match
decisions to be made externally to the network controller chip but
remains simple enough that it does not significantly increase the
network controller chip's cost or complexity.

The six I/O pins in the External Address Match Interface provide the
following capabilities:
  o  Allows the external Address Match logic to view a fully
      "digitized" version of the serial data stream currently being
      received from the LAN.  One pin provides the serial data
stream,
      and another provides a clock which can be used by the external
      Address Match logic to determine when each bit in the serial
data
      stream is valid.  Through the serial data stream, the external
      Address Match logic can observe every data bit of any frame
      received from the LAN.
  o  Allows the external Address Match logic to easily identify the
      destination address field of each frame as it is received from
      the LAN.  The network controller chip activates a "start of
      address" signal when the first bit of the frame's destination
      address field is shifted out on the serial data stream.  This
      signal is used by external Address Match logic to initiate the
      address match process for each in-coming frame.
  o  Allows the external Address Match logic to determine whether the
      current serial data stream is from a frame that was transmitted
      by the local network controller chip.  In a shared media
      environment, every node observes all the traffic on the LAN
      including traffic that originates from the local node.  This
      signal is required because the algorithms used by the external
      Address Match logic need to distinguish frames transmitted by
the
      local network controller chip.
  o  Allows the external Address Match logic to signal the network
      controller chip that the current frame should be copied.  The
      external Address Match logic asserts a "match" signal when it
      detects a frame on the serial data stream which should be
      forwarded to the host computer system.
  o  Allows the e...