Browse Prior Art Database

Ring Oscillator for Testing of Variable Delay Blocks

IP.com Disclosure Number: IPCOM000117342D
Original Publication Date: 1996-Feb-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Cecchi, DR: AUTHOR [+3]

Abstract

A method and apparatus for testing and characterization of on chip delay lines is described.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 78% of the total text.

Ring Oscillator for Testing of Variable Delay Blocks

      A method and apparatus for testing and characterization of on
chip delay lines is described.

      A common way to characterize delay is to construct a ring
oscillator or RLF from the path under test.  The frequency is then a
measure of the delay through the path, i.e., delay =(1/freq) -
overhead.  Since the overhead is also unmeasurable, no absolute
measurement is possible.

      Variable delay lines have a somewhat different situation which
make a solution to a major problem on the macro possible.  Digitally
variable delay lines are controlled by a register or counter.  Since
the normal effect of the value in the register is to control the
delay of the delay line, and the steps can be as small as 25
picoseconds, the outputs of the register and the operation of the
delay line is difficult to verify if only standard test procedures
are used.  Even external AC testing would have trouble dealing with
the small delay increments.

      This invention, which solves the problem, consists of
multiplexers and a fixed delay block whose delay might vary from chip
to chip.  To test the variable delay block, a value is scanned into
the controlling register, and the multiplexers are set so as to
convert the delay block (and a fixed delay block if necessary to
reduce the frequency) into a ring oscillator and connect it to a test
output.

      The frequency is measured.  A different value is scanned...