Browse Prior Art Database

Metastable Resistant Latch

IP.com Disclosure Number: IPCOM000117351D
Original Publication Date: 1996-Feb-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Cecchi, DR: AUTHOR [+2]

Abstract

A Bi-complementary Metal Oxide Semiconductor (BiCMOS) shift register latch with improved metastability performance is disclosed.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 90% of the total text.

Metastable Resistant Latch

      A Bi-complementary Metal Oxide Semiconductor (BiCMOS) shift
register latch with improved metastability performance is disclosed.

      In order to make this double latch design almost immune to
metastability, the following steps were considered.
  1.  Maximize the Gain Bandwith product of the L1 and L2 latches to
       optimize the fast recovery from metastability.
  2.  Put a voltage level shifter between the L1 and the L2 in such a
       way that, if L1 is in a metastable state, the L2 sees a valid
       logic level.
  3.  Buffer the output of the L2 with a Schmitt Trigger CMOS circuit
       so that if L2 becomes metastable the output of the L2 has a
valid
       logic state with fast transient response.
      o  Items 1,2,3 are the characteristics that make this design
          better then previous ones.  In addition, the next design
          precautions were taken in order to further increase the
Mean
          Time Between failures:
  4.  Use a single phase clocking scheme which utilizes very
       efficiently the 2 ns clock cycle by removing the uncertainty
       between the C (which clocks the L1) and the B (which clocks
the
       L2) clocks.
  5.  Use Bipolar devices to drive the L1 and L2.  The Bipolars make
       the transitions faster without loading the latches too much.

      In addition, I would like to men...