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Browse Prior Art Database

Method to Reduce Power Consumption of L1 and L2 Cache

IP.com Disclosure Number: IPCOM000117357D
Original Publication Date: 1996-Feb-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 93K

Publishing Venue

IBM

Related People

Miyahira, T: AUTHOR [+3]

Abstract

Disclosed is a method for reducing power consumption of L1 (Level 1) and/or L2 (Level 2) cache. The method provides the certain way to for the bus snooping in L1 and/or L2 cache. It's not necessary to keep the clock running if it's assured that any of the device drivers that can handle Direct Memory Access (DMA) transfer feature do not activate the transfer operation in the corresponding device( so-called "bus master" device or "DMA slave" device).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Method to Reduce Power Consumption of L1 and L2 Cache

      Disclosed is a method for reducing power consumption of L1
(Level 1) and/or L2 (Level 2) cache.  The method provides the certain
way to for the bus snooping in L1 and/or L2 cache.  It's not
necessary to keep the clock running if it's assured that any of the
device drivers that can handle Direct Memory Access (DMA) transfer
feature do not activate the transfer operation in the corresponding
device( so-called "bus master" device or "DMA slave" device).

      Fig. 1 shows the example of the operation flow for this method.
Fig. 2 shows the example of how to check if any device drivers
activate the DMA transfer operation.  Fig. 3 shows the example of a
hardware to restart the clock(s) of L1 and/or L2 cache.

      In Fig. 1, when Operating System (OS) scheduler detects that
there is no effective task other than just waiting for next coming
job, the system state is determined to be in Central Processing Unit
(CPU) idle (Fig. 1-1).  If it's also detected that there is no device
activity in that CPU idle, the clock(s) for the bus snooping in L1
and/or L2 cache is/are stopped to reduce the power consumption of
them (Fig. 1-2) before entering CPU sleep (Fig. 1-3) state.  Since
the base clock of the CPU is also stopped during CPU sleep period,
the CPU does not run until next external interrupt which is usually a
time tick interrupt (Fig. 1-4).  At the same time the external
interrupt occurs, the clock(s) of L1 and/or L2 cache is(are)
restarted.

      In Fig. 2, p...