Browse Prior Art Database

56/64 KBPS Automatic Speed Detection

IP.com Disclosure Number: IPCOM000117371D
Original Publication Date: 1996-Feb-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 80K

Publishing Venue

IBM

Related People

Baudelot, F: AUTHOR [+4]

Abstract

The low speed data communication network operates at 56 Kbps in the U.S. while it is 64 Kbps in EMEA. Several telecommunication protocols operate with timers. The latter are line speed dependant and must be configured at installation time. The idea is to provide an automatiline speed detection and configuration.

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56/64 KBPS Automatic Speed Detection

      The low speed data communication network operates at 56 Kbps in
the

U.S.

while it is 64 Kbps in EMEA.  Several telecommunication
protocols operate with timers.  The latter are line speed dependant
and must be configured at installation time.  The idea is to provide
an automatiline speed detection and configuration.

The advantages of the current solution are the following:
  o  The network line speed is automatically detected by hardware
  o  The software can read this information through a register and,
      therefore, is able to set-up the protocol timers accordingly
  o  Only one product whatever the country

Applications of the invention:
  o  Any telecommunication adapter using a V.24 or V.35 or X.21
      interface

      A 56/64 Kbps low speed telecommunication adapter is designed
around a Serial Communication Controller (SCC) and a microcontroller.

The clock detection logic monitors the incoming network receive_clock
and compares it to a local 64 KHz oscillator.  The output reflects
the result of the comparison and is connected to the input port 0 bit
0 of the microcontroller.  The software reads this port and
determines automatically the value of the protocol timers to be used.

Fig. 2 describes the implementation of the clock detection logic.
The incoming network receive_clock RCLK is ampled by a free-running
64 KHz clock.  To avoid metastability problem three latches are
implemented.  Q1 sa...