Browse Prior Art Database

XNOR Gate

IP.com Disclosure Number: IPCOM000117374D
Original Publication Date: 1996-Feb-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Knott, P: AUTHOR

Abstract

Disclosed is a fast XNOR circuit which exceeds the performance of existing circuits and is yet advantageous with respect to area consumption. This XNOR distinguishes itself from existing circuits by a fast switching time which stays within a tight range for all possible input conditions.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 61% of the total text.

XNOR Gate

      Disclosed is a fast XNOR circuit which exceeds the performance
of existing circuits and is yet advantageous with respect to area
consumption.  This XNOR distinguishes itself from existing circuits
by a fast switching time which stays within a tight range for all
possible input conditions.

      With regard to the Figure, two cross-coupled complementary pass
gates (TP0/TN0 and TP1/TN1) and two N-channel devices TN3 and TN4
perform the XOR function.  Output buffer TP5 and TN5 isolate the
inputs from the output and provides sufficient output drive
capability for this circuit to be cascaded for a fast XOR-Tree or to
interface with standard logic books.

This is the truth table for this circuit:
                Input A     Input B     Output
                   0           0           1
                   1           0           0
                   0           1           0
                   1           1           1

      The internal node performs a full voltage swing for all input
conditions providing always a full drive signal to the output buffer.
For the input condition Input A = Input B = 1 (up-level) devices TN3
and TN4 will fully discharge the internal node while for the input
condition Input A = Input B = 0 (low-level) the N-channel pass gate
devices TN0 and TN1 ass...