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Variable Delay Book

IP.com Disclosure Number: IPCOM000117375D
Original Publication Date: 1996-Feb-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Cecchi, DR: AUTHOR [+3]

Abstract

Described is a Complementary Metal Oxide Semiconductor (CMOS) buffer or inverter whose delay is selectable to one of two values, the difference between which is chosen at design time. It may be arbitrarily small. Which delay is obtained, is selected by a control input.

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Variable Delay Book

      Described is a Complementary Metal Oxide Semiconductor (CMOS)
buffer or inverter whose delay is selectable to one of two values,
the difference between which is chosen at design time.  It may be
arbitrarily small.  Which delay is obtained, is selected by a control
input.

      In this approach, a logic block (inverter) is created whose
delay is switchable between two values by means of a control input.
The differences are typically in the range of 25 to 400 ps.  This is
very useful in constructing a delay locked loop, for example.  Delay
locked loops are useful in such things as finding the middle of the
data window on a Scalable Coherent Interface (SCI) input line.  Or
for standard SCI for that matter.

      The first block is a sort of tri-state buffer.  When it is
nonconductive, the rise time and delay of the circuit is increased.
When it is conductive, the drive to the load is increased, and the
delay is decreased.  The control input causes the delay to change
(Figure).