Browse Prior Art Database

Lempel-Ziv-Blender-Wolf High-Speed Data Compression Circuit

IP.com Disclosure Number: IPCOM000117392D
Original Publication Date: 1996-Feb-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Satoh, A: AUTHOR

Abstract

Disclosed is an Lempel-Ziv-Blender-Wolf (LZBW) high-speed data compression circuit. In LZBW compression, input data are searched for in a history buffer, and the difference in length between the longest and second-longest match data items is calculated. The data are then coded as the pointer to the longest match data item and the difference in length. In decompression, the data are output from the history buffer indicated by the pointer, and simultaneously searched for in the buffer, to find the longest match data item. When it is found, more data are output according to the difference in length.

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Lempel-Ziv-Blender-Wolf High-Speed Data Compression Circuit

      Disclosed is an Lempel-Ziv-Blender-Wolf (LZBW) high-speed
data compression circuit.  In LZBW compression, input data are
searched for in a history buffer, and the difference in length
between the longest and second-longest match data items is
calculated.  The data are then coded as the pointer to the longest
match data item and the difference in length.  In decompression, the
data are output from the history buffer indicated by the pointer, and
simultaneously searched for in the buffer, to find the longest match
data item.  When it is found, more data are output according to the
difference in length.

      Figs. A-D illustrate the concept of the new scheme with
examples.  The scheme includes a Content-Addressable Memory (CAM) for
the history buffer, two priority encoders (P-ENC1 and P-ENC2), an
address comparator (CMP), two counters (CNT1 and CNT2) and a latch
(LATCH).  Lower addresses have higher priority in P-ENC1, while
higher addresses have higher priority in P-ENC2.

      In Fig. A, the addresses 0, 2, and 5 match the input data item
'A', and the matching addresses MADR1=0 and MADR2=5 are output from
P-ENC1 and P-ENC2, respectively.  When the matching signal MSIG goes
to 1, the counter CNT1 is enabled to count up the matching length
MLEN.  IF MADR1 is different from MADR2, CMP keeps the reset signal
to 1, and CNT2 is disabled.

      In Fig. B, addresses 1, 3, and 6 match the da...