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Duty Cycle Correction and Frequency Multiplication Using Delay-Locked Loops

IP.com Disclosure Number: IPCOM000117417D
Original Publication Date: 1996-Feb-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 87K

Publishing Venue

IBM

Related People

Dieffenderfer, JN: AUTHOR [+2]

Abstract

VLSI integrated circuits have progressed to a level of sophistication and performance such that the requirements placed on system clocks now include 50/50 duty cycles and/or the need for frequency multiplication and multiple phased clocks. Precision oscillators with 50/50 duty cycles are prohibitively expensive for products targeted for the consumer market; e.g., set-top boxes, PDA's, Multi-media PC's, video games, notebook computers. Clock squaring and frequency multiplication have classically been handled by Phase-Locked Loops (PLL). These circuits have intricate design requirements, take up a significant amount of chip area, and their VCO's are susceptible to noise. These disadvantages make PLL's expensive to develop and expensive to implement in terms of silicon area.

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Duty Cycle Correction and Frequency Multiplication Using Delay-Locked
Loops

      VLSI integrated circuits have progressed to a level of
sophistication and performance such that the requirements placed on
system clocks now include 50/50 duty cycles and/or the need for
frequency multiplication and multiple phased clocks.  Precision
oscillators with 50/50 duty cycles are prohibitively expensive for
products targeted for the consumer market; e.g., set-top boxes,
PDA's, Multi-media PC's, video games, notebook computers.  Clock
squaring and frequency multiplication have classically been handled
by Phase-Locked Loops (PLL).  These circuits have intricate design
requirements, take up a significant amount of chip area, and their
VCO's are susceptible to noise.  These disadvantages make PLL's
expensive to develop and expensive to implement in terms of silicon
area.  In addition, PLL lock time for cold start is typically 10us
which is an undesirable amount of time to wait for processors that
are interrupt latency sensitive.

      The disclosed circuit uses a Delay-Locked Loop (DLL) with
the topology depicted in Fig. 1.  The circuit of Fig. 2 performs duty
cycle correction as depicted in the first four lines of the timing
diagram in Fig. 4.  The "raw" clock is first fed to clock input of a
positive-edge triggered divide-by-two circuit whose output will
change states every time a clock edge occurs.  The resulting output
signal is a 50/50 duty cycle clock whose period is 2T, twice the
original or "raw" clock period T.  The square clock is now used as
the input to the DLL circuit.  The DLL ...