Browse Prior Art Database

Control System for Unexpected, Continuous or Over Authorized Rate Interrupts

IP.com Disclosure Number: IPCOM000117425D
Original Publication Date: 1996-Feb-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Benayoun, A: AUTHOR [+4]

Abstract

The proposed system allows to stop unexpected interrupts in a multi-adapter environment in order to let all nonfailing adapters working by disabling the failing adapter as long as it fails.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 65% of the total text.

Control System for Unexpected, Continuous or Over Authorized Rate
Interrupts

      The proposed system allows to stop unexpected interrupts in a
multi-adapter environment in order to let all nonfailing adapters
working by disabling the failing adapter as long as it fails.

Advantage of the solution are:
  - Reliable
  - Dynamic change on both sense:  disable and enable.
  - Applicable to all multi-tasking communication products

Two basic functions are implemented:
  1.  A background task; low-priority task that gets control when the
       processor is waiting.
  2.  A NMI interrupt routine:  The Non Maskable Interrupt routine is
       dedicated to disaster processes.  It gets control when
something
       abnormal occurs.

Background task process - When the processor is waiting for action it
runs the background task that performs various checking like memory
checksum, looks at interrupt counters if some are disabled and may be
reactivated, and performs a reset of the watchdog timer avoiding NMI
interrupt to occur.

      In this peculiar case, interrupt counters may be attached to
each interrupt source in order to count them even if not used.  This
will allow to reactivate the failing interrupt when the normal
situation comes back.

      Where is counter function is not available, an internal timer
may be used to try to reestablish interrupt sources after some delay
(1mn for example).  If this interrupt continues to fail, the NMI
r...