Browse Prior Art Database

VHDL - Simulation Coverage Improvement

IP.com Disclosure Number: IPCOM000117440D
Original Publication Date: 1996-Feb-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 97K

Publishing Venue

IBM

Related People

Benayoun, A: AUTHOR [+5]

Abstract

Disclosed is a program which analyzes the paths state in a VHDL simulation and provides statistical information to the logical designer to help him in writing efficient test cases to have a better coverage.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

VHDL - Simulation Coverage Improvement

      Disclosed is a program which analyzes the paths state in a VHDL
simulation and provides statistical information to the logical
designer to help him in writing efficient test cases to have a better
coverage.

      Statistics may be obtained for the whole Structure and/or for
individual Islands if the structure is comprised of several ones.
The program is "open" which means that new rules can be added easily
and selected by the designer on option.

The advantages of the current solution are the following:
  o  Provide the logical designers with statistical data and hints
      to show up unexercised logic during simulation
  o  New rules can easily be added to the program
  o  The program can generate statistics on only exercised,
      unexercised or flagged paths or all cases (a path is flagged by
      the designer when he does not want it to appear in the
coverage).
      It can produce a verbose output in which all the paths are
      detailed (labels, decision elements content, etc.).
  o  The program can generate for each path the list of assignments
it
      leads to.  The designer may easily find conditions on some
better
      known signals
  o  The program can give for each assignment the list of paths that
      lead to it.  The designer will treat first those who have the
      highest sink number.  This also gives an information on the
logic
      parts that are less well simulated if many of the assignments
are
      in the same logic zone
  o  The program can generate an ordered list of the most often
      unexercised decision elements.  These elements can belong to
      several paths.  The designer should look at those who are the
      most often used to see if the test case simply misses to
activate
      them.  Moreover some of them may show simple conditions to be
      activated.
  o  The program can generate a list of the unexercised decision
      blocks that reference structure primary inputs.  Conditions on
      primary inputs are easier to find and can be set by test case.
  o  The program can produce a list giving (if any) all the Paths
      included in other ones, with a statistic on the number of times
      each Path is included in other ones.  A path can be included in
      another one if it leads to assignments of both latches and
      internal signals.  Working on the most often included paths
first
      may cause the including path activation, and conditions on them
      are easier to find.  The designer begins to treat the paths
that
      are most often included.

Applications of the invention:
  o  Any development of VLSI chips using VHDL language

Following is an example of the program output:
                   COVERAG...