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Printed Wiring Board Common Circuitized Core by Front/Back Panel Layout

IP.com Disclosure Number: IPCOM000117442D
Original Publication Date: 1996-Feb-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 75K

Publishing Venue

IBM

Related People

Takahashi, K: AUTHOR [+2]

Abstract

Disclosed is a Printed Wiring Board (PWB) panel layout which enables the use of common circuitized core in multi-layer PWBs produced by pin lamination process.

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Printed Wiring Board Common Circuitized Core by Front/Back Panel
Layout

      Disclosed is a Printed Wiring Board (PWB) panel layout which
enables the use of common circuitized core in multi-layer PWBs
produced by pin lamination process.

      Fig. 1 shows an example of cross section for multi-layer PWB
which is produced by pin lamination and has two cores in the internal
layer.  In panel layout shown in Fig. 2, the art work of S2 layer (1)
and S3 layer (4) is different.  The art work of P1 (2) and P2 layer
(3) is also different.  Therefore, core-1 (5) and core-2 (6) are
circuitized separately.

      Fig. 3 shows panel layout of this disclosure.  Fig. 4 shows
multi-layer structure in this panel layout.  In Fig. 4, core-1 (7) is
same as core-2 (8).  Therefore, common circuitized core is able to be
used for core-1 and core-2.

      In Fig. 4, signal layer-1 (9) and signal layer-2 (10) are the
same.  Therefore, common film and/or glass master for signal layer-1
and signal layer-2 is also applicable.