Browse Prior Art Database

Power Management Suspend/Resume for 603 Processor

IP.com Disclosure Number: IPCOM000117449D
Original Publication Date: 1996-Feb-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 6 page(s) / 182K

Publishing Venue

IBM

Related People

Lam, SH: AUTHOR [+3]

Abstract

A method to put the PowerPC* 603 system in the Power Management (PM) Suspend mode. The system is entered the Suspend mode when the Suspend events occurred to reduce the system power consumption.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 34% of the total text.

Power Management Suspend/Resume for 603 Processor

      A method to put the PowerPC* 603 system in the Power Management
(PM) Suspend mode.  The system is entered the Suspend mode when the
Suspend events occurred to reduce the system power consumption.

      The most effective way to reduce the power consumption of a
system is to put it in the Suspend mode.  The Suspend mode is the
minimum power mode, normally considered off, where the system can
still be brought back to the application it was executing just prior
to entering the Suspend mode.  Power is removed from all subsystems,
the CPU is powered off, oscillators are depowered, but the memory
subsystem and video subsystem are kept alive.  In the Suspend mode,
the PM chip waits for an event to resume the system back into the
active mode.  The Suspend mode is entered under control of PM
software.  A Power Management Interrupt (PMI) indicating the need to
enter the Suspend mode may be generated in a number of Suspend
events:
  o  The Suspend timer is time out.
  o  By the assertion of an External PMI signal from the H8
      microcontroller.  The following Suspend events are detected by
H8:
     -  Battery power source does not have enough power to support a
         running system.
     -  Opening the built-in keyboard of the battery powered system's
         case.
     -  Closing the lid of the battery powered system's case.
  o  Beside the above hardware supports, the software also detects
      Suspend event such as user selecting a Suspend icon.
  Bit 0-1:  HOST_SUSSTAT# to SUSSTAT#.  These two bits (HS1 is the
             MSB) control the timing from HOST_SUSSTAT# to SUSSTAT#
             signal during Suspend mode.  This timing allows the
             memory controller to switch from normal to Suspend mode.
             These bits are described below:
              00: 1 RTCCLK, 01: 2 RTCCLKs (default), 10: 4 RTCCLKs,
               11: 8 RTCCLKs
  Bit 2-3:  SUSSTAT# to HOST_SUSSTAT#.  These two bits (SH1 is the
             MSB) control the timing from SUSSTAT# to HOST_SUSSTAT#
             signal during Resume process.  This timing allows the
             system oscillators to reach their stable frequencies.
             These bits are described below:
              00: 30mS (default), 01: 100mS, 10: 200mS, 11: 400mS
  Bit 4-5:  RSM_RST# Pulse Width.  These two bits (RP1 is the MSB)
             control the timing of the RSM_RST# pulse width.  This
             timing allows devices on the PCI and ISA bus to reset.
             These bits are described below:
              00: 1mS (default), 01: 2mS, 10: 4mS, 11: 8mS
  Bit 6-7:  Reserved.

Suspend Sequence

The following events take place when a system entered its Suspend
mode...