Browse Prior Art Database

Transmit Ready Queue Address Generation and Management for Asynchronous Transfer Mode Traffic

IP.com Disclosure Number: IPCOM000117458D
Original Publication Date: 1996-Feb-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 174K

Publishing Venue

IBM

Related People

Barker, KJ: AUTHOR [+4]

Abstract

Described is a "Transmit Ready Queue (TRQ) Address Generation" apparatus which is located in the ATM adapter and is used by the ATM device driver to queue requests for frame transmission. The device driver interace to this apparatus consists of a fixed set of host addresses. When accessed by the device driver, this apparatus will generate physical addresses for accessing the TRQ located in the ATM adapter memory. The apparatus also manages the queue as a circular FIFO. It indicates when the queue is full, and wraps back to the first queue loation after an entry has been placed in the last queue location.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 44% of the total text.

Transmit Ready Queue Address Generation and Management for Asynchronous
Transfer Mode Traffic

      Described is a "Transmit Ready Queue (TRQ) Address Generation"
apparatus which is located in the ATM adapter and is used by the ATM
device driver to queue requests for frame transmission.  The device
driver interace to this apparatus consists of a fixed set of host
addresses.  When accessed by the device driver, this apparatus will
generate physical addresses for accessing the TRQ located in the ATM
adapter memory.  The apparatus also manages the queue as a circular
FIFO.  It indicates when the queue is full, and wraps back to the
first queue loation after an entry has been placed in the last queue
location.  The entries in the Transmit Ready Queue tell the ATM
adapter hardware which ATM Virtual Channel Connection (VCC) is
associated with the frame being queued for transmission and where in
the host memory the buffer descriptor for the first frame is located.
Since buffer descriptors can be linked together, a single entry in
the TRQ can queue multiple frames for transmission.

      The advantage of this method over others is that it provides
a fast, efficient, and simple method of allowing the device driver to
place entries on the TRQ without the large overhead associated with
managing the TRQ.  A single set of host bus I/O addresses are used by
the device driver to place entries on the TRQ while the TRQ Address
Generation apparatus manages the queue by placing the new entry in
the next available queue location.

      Fig. 1 shows the mapping of the ATM adapter into the I/O
address space of the host system.  The values of the I/O addresses
used by the TRQ Address Generation apparatus are determined at system
initialization.  The TRQ is located in the adapter's memory and the
TRQ Address Generation apparatus is responsible for moving the
contents of the TRQ entries into their proper memory location.  Fig.
1 shows an example of a system with a 16 bit data bus, like ISA, and
two instances of the TRQ Address Generation apparatus.  Each TRQ I/O
interface consists of three addresses.  In the case of the AAL1 TRQ,
these three addresses, TRQ_AAL1_LC, TRQ_AAL1_TFDAh, and
TRQ_AAL1_TFDAl are used by the device driver to place entries on the
AAL1 TRQ.  The TRQ_AAL1_LC address is used to write the ATM logical
channel number, indicating the VCC, into the AAL1 TRQ.  The
TRQ_AAL1_TFDAh and TQ_AAL1_TFDAl addresses are used to write the 24
bit host address of the transmit buffer descriptor into the queue.
Since this example shows an architecture with a 16 bit data path, two
addresses are required for the descriptor address information.
Systems with a 3 bit data path, like PCI, would only require one I/O
address for the descriptor information.  A second TRQ interface is
provided for AL5 traffic.  This allows the adapter to prioritize the
transmissio of one frame type over the other.  The addresses
associated with the AAL5 TRQ are us...